Editing renesas/r-car/h1

{{renesas title|R-Car H1}}
{{mpu
|name=R-Car H1
|image=r-car h1.png
|designer=Renesas
|designer 2=ARM Holdings
|manufacturer=TSMC
|model number=H1
|part number=R8A77790
|market=Embedded
|first announced=October 21, 2011
|first launched=November, 2011
|family=R-Car
|series=1st Gen
|frequency=800 MHz
|frequency 2=1000 MHz
|isa=ARMv7
|isa family=ARM
|microarch=Cortex-A9
|microarch 2=SH-4A
|core name=Cortex-A9
|core name 2=SH-4A
|process=40 nm
|technology=CMOS
|word size=32 bit
|core count=5
|thread count=5
|max cpus=1
|max memory=2 GiB
|v core=1.2 V
|v io=3.3 V
|package module 1={{packages/renesas/fcbga-832}}
}}
'''R-Car H1''' is a high-end embedded [[penta-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. While mass production was scheduled to begin in December 2012, it's unknown if that stage was ever actually reached. The H1 features [[5 cores]], four {{armh|Cortex-A9|l=arch}} cores operating at 1 GHz and an additional {{renesas|SH-4A|l=arch}} core operating at 800 MHz intended for real-time processing multimedia engine (MME). This chip incorporates [[Imagination]]'s {{imgtec|PowerVR SGX543}}-MP2 [[GPU]]. The H1 supports up to 2 GiB of DDR3-1066 memory.

== Cache ==
{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
{{cache size
|l1 cache=256 KiB
|l1i cache=128 KiB
|l1i break=4x32 KiB
|l1d cache=128 KiB
|l1d break=4x32 KiB
|l2 cache=1 MiB
|l2 break=4x256 KiB
}}

== Memory controller ==
{{memory controller
|type=DDR3-1066
|ecc=No
|max mem=2 GiB
|controllers=1
|channels=2
|width=32 bit
|max bandwidth=7.95 GiB/s
|bandwidth schan=3.97 GiB/s
|bandwidth dchan=7.95 GiB/s
}}

== Expansions ==
{{expansions
| pcie revision      = 2.0
| pcie lanes         = 1
| pcie config        = 1x1
| usb revision       = 2.0
| usb ports          = 2
| usb rate           = 480 Mbps
| uart               = Yes
| uart ports         = 8
| sata revision      = 3.0
| sata ports         = 1
| i2c                = Yes
| i2c ports          = 4
| gp io              = Yes
| jtag               = Yes
}}
* 3 x HSPI
* MLB (MOST150) 6-Pin I/F
* 2 x CAN 32 Message Buffers
* MMC
* 4 x SD

== Graphics ==
* Display out × 2 ch (RGB888)
* Video input x 2 ch
* Video decode processor (H.264/AVC, MPEG-4, VC-1)
{{integrated graphics
| gpu                 = PowerVR SGX543
| designer            = Imagination Technologies
| execution units     = 2
| max displays        = 2
| frequency           = 250 MHz

| opengl es ver       = 2.0
| opengl ver          = 2.0
| opencl ver          = 1.1
| directx             = 9.0 L1
}}

== Audio ==
* Sound processing unit × 2 ch
* Sampling rate converter × 10 ch
* Sound serial interface × 10 ch
* MOST DTCP

== Features == 
{{arm features
|thumb=No
|thumb2=Yes
|thumbee=Yes
|vfpv1=No
|vfpv2=No
|vfpv3=Yes
|vfpv3-d16=No
|vfpv3-f16=No
|vfpv4=No
|vfpv4-d16=No
|vfpv5=No
|neon=Yes
|jazelle=Yes
|wmmx=No
|wmmx2=No
}}

== Block Diagram ==
: [[File:rcar h1.gif]]
@@ Line 1: / Line 1: @@
 {{renesas title|R-Car H1}}
-{{chip
+{{mpu
 |name=R-Car H1
 |image=r-car h1.png
@@ Line 32: / Line 32: @@
 |package module 1={{packages/renesas/fcbga-832}}
 }}
-'''R-Car H1''' is a high-end embedded [[penta-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The H1 features [[5 cores]], four {{armh|Cortex-A9|l=arch}} cores operating at 1 GHz and an additional {{renesas|SH-4A|l=arch}} core operating at 800 MHz intended for real-time processing multimedia engine (MME). This chip incorporates [[Imagination]]'s {{imgtec|PowerVR SGX543}}-MP2 [[GPU]]. The H1 supports up to 2 GiB of dual-channel DDR3-1066 memory.
+'''R-Car H1''' is a high-end embedded [[penta-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. While mass production was scheduled to begin in December 2012, it's unknown if that stage was ever actually reached. The H1 features [[5 cores]], four {{armh|Cortex-A9|l=arch}} cores operating at 1 GHz and an additional {{renesas|SH-4A|l=arch}} core operating at 800 MHz intended for real-time processing multimedia engine (MME). This chip incorporates [[Imagination]]'s {{imgtec|PowerVR SGX543}}-MP2 [[GPU]]. The H1 supports up to 2 GiB of DDR3-1066 memory.
-Announced in late 2011, Renesas expected mass production begin in December 2012 with a peak rate of 100,000 units per month by December 2013.
 == Cache ==
@@ Line 42: / Line 40: @@
 |l1i cache=128 KiB
 |l1i break=4x32 KiB
-|l1i desc=4-way set associative
 |l1d cache=128 KiB
 |l1d break=4x32 KiB
-|l1d desc=4-way set associative
 |l2 cache=1 MiB
 |l2 break=4x256 KiB
@@ Line 129: / Line 125: @@
 == Block Diagram ==
-: [[File:rcar h1 block.png|650px]]
+: [[File:rcar h1.gif]]
-: [[File:r-car h1 block.png|650px]]
-== Dev Board ("MARZEN") ==
-* 200 mmx 150 mm
-* R-CAR H1
-* 64 MiB flash memory
-* 1 MiB serial flash/E²PROM
-* 2 x512 MiB DDR3-DRAM
-* RS-232C, UART,USB, SD, LAN, SATA, PCI, CAN, and MLB interfaces
-* Analog RGB with DSUB 15-pin and/or LVDS flat cable connector
-* switches,LEDs, I/O expansion
-: [[File:renesas marzen h1 board.png|450px]]
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	R-Car H1 - Renesas#package + and R-Car H1 - Renesas#io +
base frequency	800 MHz (0.8 GHz, 800,000 kHz) + and 1,000 MHz (1 GHz, 1,000,000 kHz) +
core count	5 +
core name	Cortex-A9 + and SH-4A +
core voltage	1.2 V (12 dV, 120 cV, 1,200 mV) +
designer	Renesas + and ARM Holdings +
family	R-Car +
first announced	October 21, 2011 +
first launched	November 2011 +
full page name	renesas/r-car/h1 +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	PowerVR SGX543 +
integrated gpu base frequency	250 MHz (0.25 GHz, 250,000 KHz) +
integrated gpu designer	Imagination Technologies +
integrated gpu execution units	2 +
io voltage	3.3 V (33 dV, 330 cV, 3,300 mV) +
isa	ARMv7 +
isa family	ARM +
l1$ size	256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	4-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	4-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate	November 2011 +
main image	+
manufacturer	TSMC +
market segment	Embedded +
max cpu count	1 +
max memory	2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory bandwidth	7.95 GiB/s (8,140.8 MiB/s, 8.536 GB/s, 8,536.248 MB/s, 0.00776 TiB/s, 0.00854 TB/s) +
max memory channels	2 +
max pcie lanes	1 +
microarchitecture	Cortex-A9 + and SH-4A +
model number	H1 +
name	R-Car H1 +
package	FCBGA-832 +
part number	R8A77790 +
process	40 nm (0.04 μm, 4.0e-5 mm) +
series	1st Gen +
smp max ways	1 +
supported memory type	DDR3-1066 +
technology	CMOS +
thread count	5 +
word size	32 bit (4 octets, 8 nibbles) +