From WikiChip
Difference between revisions of "qualcomm/microarchitectures/cloud ai 100"
< qualcomm

(outline)
Line 16: Line 16:
 
}}
 
}}
 
'''Cloud AI 100''' is an [[NPU]] microarchitecture designed by [[Qualcomm]] for the server and edge market. Those NPUs are sold under the {{qualcomm|Cloud AI}} brand.
 
'''Cloud AI 100''' is an [[NPU]] microarchitecture designed by [[Qualcomm]] for the server and edge market. Those NPUs are sold under the {{qualcomm|Cloud AI}} brand.
 +
 +
== Process Technology ==
 +
The Cloud AI 100 SoC is fabricated on TSMC's [[7-nanometer process]].
 +
 +
== Architecture ==
 +
 +
=== Key Features ===
 +
 +
== Block Diagram ==
 +
 +
=== SoC ===
 +
 +
=== AI Core ===
 +
 +
== Memory Hierarchy ==
 +
 +
== Overview ==
 +
 +
== AI Core ==
 +
 +
== Performance claims ==
 +
 +
== Bibliography ==
 +
* Linley Fall Processor Conference 2021
 +
* {{bib|hc|33|Qualcomm}}

Revision as of 06:06, 15 September 2021

Edit Values
Cloud AI 100 µarch
General Info
Arch TypeNPU
DesignerQualcomm
ManufacturerTSMC
IntroductionMarch, 2021
Process7 nm
PE Configs16
Pipeline
TypeVLIW
Decode4-way
Cache
L2 Cache1 MiB/core
Side Cache8 MiB/core

Cloud AI 100 is an NPU microarchitecture designed by Qualcomm for the server and edge market. Those NPUs are sold under the Cloud AI brand.

Process Technology

The Cloud AI 100 SoC is fabricated on TSMC's 7-nanometer process.

Architecture

Key Features

Block Diagram

SoC

AI Core

Memory Hierarchy

Overview

AI Core

Performance claims

Bibliography

  • Linley Fall Processor Conference 2021
  • Qualcomm, IEEE Hot Chips 33 Symposium (HCS) 2021.
Retrieved from "https://en.wikichip.org/w/index.php?title=qualcomm/microarchitectures/cloud_ai_100&oldid=99313"
Facts about "Cloud AI 100 - Microarchitectures - Qualcomm"
RDF feed
codenameCloud AI 100 +
designerQualcomm +
first launchedMarch 2021 +
full page namequalcomm/microarchitectures/cloud ai 100 +
instance ofmicroarchitecture +
manufacturerTSMC +
nameCloud AI 100 +
process7 nm (0.007 μm, 7.0e-6 mm) +
processing element count16 +