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{{pezy title|PEZY-SCnp}} | {{pezy title|PEZY-SCnp}} | ||
− | {{ | + | {{mpu |
|name=PEZY-SCnp | |name=PEZY-SCnp | ||
− | |image=pezy-scnp | + | |image=pezy-scnp.png |
+ | |image size=300px | ||
|designer=PEZY | |designer=PEZY | ||
|manufacturer=TSMC | |manufacturer=TSMC | ||
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|first announced=May 6, 2016 | |first announced=May 6, 2016 | ||
|first launched=May 6, 2016 | |first launched=May 6, 2016 | ||
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|frequency=766.66 MHz | |frequency=766.66 MHz | ||
|process=28 nm | |process=28 nm | ||
|technology=CMOS | |technology=CMOS | ||
− | | | + | |die area=411.6 mm² |
− | | | + | |die length=19.5 mm |
+ | |die width=21.1 mm | ||
+ | |core count=1024 | ||
|power=100 W | |power=100 W | ||
− | + | |v core=0.9 V | |
− | |v core=0. | ||
− | |||
|electrical=Yes | |electrical=Yes | ||
|packaging=Yes | |packaging=Yes | ||
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|socket 0 type=BGA | |socket 0 type=BGA | ||
}} | }} | ||
− | '''PEZY-SCnp''' (SC - '''Super Computer'''; np - '''New Package''') is a revised version of the {{pezy|PEZY-SC}} model by [[PEZY]] introduced in may of 2016 | + | '''PEZY-SCnp''' (SC - '''Super Computer'''; np - '''New Package''') is a revised version of the {{pezy|PEZY-SC}} model by [[PEZY]] introduced in may of 2016. The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. The PEZY-SCnp is said to deliver 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. As with the PEZY-SC, the SCnp is also manufactured on TSMC's 28HPC+ ([[28 nm process]]). |
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== Architecture == | == Architecture == | ||
− | {{ | + | {{main|pezy/pezy-sc#Architecture|l1=PEZY-SC §Architecture}} |
The PEZY-SCnp's architecture is identical to the {{pezy|PEZY-SC}}. | The PEZY-SCnp's architecture is identical to the {{pezy|PEZY-SC}}. | ||
== Cache == | == Cache == | ||
PEZY-SC's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared). | PEZY-SC's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared). | ||
− | {{cache | + | {{cache info |
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|l1i cache=2 MiB | |l1i cache=2 MiB | ||
|l1i break=1024x2 KiB | |l1i break=1024x2 KiB | ||
− | |l1i | + | |l1i extra=(per processor element) |
|l1d cache=1 MiB | |l1d cache=1 MiB | ||
|l1d break=512x2 KiB | |l1d break=512x2 KiB | ||
− | |l1d | + | |l1d extra=(per 2 processor elements) |
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|l2 cache=4 MiB | |l2 cache=4 MiB | ||
|l2 break=4x2 MiB | |l2 break=4x2 MiB | ||
− | |l2 | + | |l2 extra=(per city) |
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|l3 cache=8 MiB | |l3 cache=8 MiB | ||
|l3 break=4x2 MiB | |l3 break=4x2 MiB | ||
− | |l3 | + | |l3 extra=(per prefecture) |
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}} | }} | ||
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== Memory controller == | == Memory controller == | ||
− | {{memory controller | + | {{integrated memory controller |
− | |type=DDR4- | + | | type = DDR4-1866 |
− | + | | controllers = 1 | |
− | |controllers= | + | | channels = 8 |
− | |channels=8 | + | | ecc support = <!-- ?? --> |
− | | | + | | bandwidth schan = 14,933 MB/s |
− | + | | bandwidth dchan = 29,866 MB/s | |
− | |bandwidth schan= | + | | bandwidth qchan = 59,732 MB/s |
− | |bandwidth dchan= | + | | bandwidth ochan = 119,464 MB/s |
− | |bandwidth qchan= | + | | max memory = |
− | |bandwidth | ||
− | | | ||
}} | }} | ||
== Expansions == | == Expansions == | ||
− | {{expansions | + | {{mpu expansions |
− | | | + | | pcie revision = 3.0 |
− | + | | pcie lanes = 8 | |
− | | | + | | pcie config = |
− | |pcie | + | | pcie config 1 = |
− | |pcie | + | | pcie config 2 = |
− | |pcie config= | + | | usb revision = |
− | + | | usb revision 2 = | |
+ | | usb ports = | ||
+ | | sata revision = | ||
+ | | sata ports = | ||
+ | | integrated lan = | ||
+ | | uart = Yes | ||
+ | | gp io = Yes | ||
}} | }} |
Facts about "PEZY-SCnp - PEZY"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | PEZY-SCnp - PEZY#pcie + and PEZY-SCnp - PEZY#package + |
base frequency | 766.66 MHz (0.767 GHz, 766,660 kHz) + |
core count | 1,024 + |
core voltage | 0.95 V (9.5 dV, 95 cV, 950 mV) + |
designer | PEZY + |
family | PEZY-SCx + |
first announced | May 6, 2016 + |
first launched | May 6, 2016 + |
full page name | pezy/pezy-scx/pezy-scnp + |
has ecc memory support | true + |
instance of | microprocessor + |
l1$ size | 64 KiB (65,536 B, 0.0625 MiB) + and 3,072 KiB (3,145,728 B, 3 MiB) + |
l1d$ description | per 2 processor elements + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + and 1,024 KiB (1,048,576 B, 1 MiB) + |
l1i$ description | per processor element + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + and 2,048 KiB (2,097,152 B, 2 MiB) + |
l2$ description | per city + |
l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + and 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |
l3$ description | per prefecture + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
ldate | May 6, 2016 + |
main image | + |
manufacturer | TSMC + |
market segment | Supercomputer + |
max memory bandwidth | 127.156 GiB/s (130,207.744 MiB/s, 136.533 GB/s, 136,532.715 MB/s, 0.124 TiB/s, 0.137 TB/s) + |
max memory channels | 8 + |
model number | PEZY-SCnp + |
name | PEZY-SCnp + |
package | FCBGA-2397 + |
peak flops (double-precision) | 1,570,133,331,968 FLOPS (1,570,133,331.968 KFLOPS, 1,570,133.332 MFLOPS, 1,570.133 GFLOPS, 1.57 TFLOPS, 0.00157 PFLOPS, 1.570133e-6 EFLOPS, 1.570133e-9 ZFLOPS) + |
peak flops (single-precision) | 3,140,266,663,936 FLOPS (3,140,266,663.936 KFLOPS, 3,140,266.664 MFLOPS, 3,140.267 GFLOPS, 3.14 TFLOPS, 0.00314 PFLOPS, 3.140267e-6 EFLOPS, 3.140267e-9 ZFLOPS) + |
power dissipation | 100 W (100,000 mW, 0.134 hp, 0.1 kW) + |
power dissipation (average) | 70 W (70,000 mW, 0.0939 hp, 0.07 kW) + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |
supported memory type | DDR4-2133 + |
technology | CMOS + |
thread count | 8,192 + |