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{{pezy title|PEZY-SCnp}}
 
{{pezy title|PEZY-SCnp}}
−
{{chip
+
{{mpu
−
|name=PEZY-SCnp
+
| name               = PEZY-SCnp
−
|image=pezy-scnp (front).png
+
| no image           = Yes
−
|designer=PEZY
+
| image              =
−
|manufacturer=TSMC
+
| image size          =
−
|model number=PEZY-SCnp
+
| caption            =  
−
|market=Supercomputer
+
| designer           = PEZY
−
|first announced=May 6, 2016
+
| manufacturer       = TSMC
−
|first launched=May 6, 2016
+
| model number       = PEZY-SCnp
−
|family=PEZY-SCx
+
| part number        =
−
|frequency=766.66 MHz
+
| market             = Industrial
−
|process=28 nm
+
| first announced     = May 6, 2016
−
|technology=CMOS
+
| first launched     = May 6, 2016
−
|core count=1,024
+
| last order          =
−
|thread count=8,192
+
| last shipment      =
−
|power=100 W
+
 
−
|average power=70 W
+
| family             =
−
|v core=0.95 V
+
| series              =
−
|package module 1={{packages/pezy/fcbga-2397}}
+
| locked              =  
−
|electrical=Yes
+
| frequency           = 766.66 MHz
−
|packaging=Yes
+
| bus type            =
−
|package 0=fcBGA-2397
+
| bus speed          = 66.66 MHz
−
|package 0 type=fcBGA
+
| bus rate            =
−
|package 0 pins=2,397
+
| clock multiplier    = 11.5
−
|package 0 pitch=1 mm
+
 
−
|package 0 width=50 mm
+
| microarch          =
−
|package 0 length=50 mm
+
| platform            =
−
|socket 0=BGA-2397
+
| chipset            =
−
|socket 0 type=BGA
+
| core name          =
−
}}
+
| core family        =
−
'''PEZY-SCnp''' (SC - '''Super Computer'''; np - '''New Package''') is a revised version of the {{pezy|PEZY-SC}} model by [[PEZY]] introduced in may of 2016. The new chip, which made use of a slightly different package in order to address a number of signal-related issues (DRAM/PCIe signal failures). The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. Operating at 766 MHz, the processor has a peak performance of 3.14 [[TFLOPS]] (single-precision) and 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. As with the PEZY-SC, the SCnp is also manufactured on [[28 nm process|TSMC's 28HPC+]].
+
| core model          =
−
{{#set:
+
| core stepping      =
−
| peak flops (single-precision) = {{#expr:766666666 * 4 * 1024}} FLOPS
+
| process             = 28 nm
−
| peak flops (double-precision) = {{#expr:766666666 * 2 * 1024}} FLOPS
+
| transistors        =
 +
| technology         = CMOS
 +
| die area            = 411.6 mm²
 +
| die width          = 21.1 mm
 +
| die length          = 19.5 mm
 +
| word size          =
 +
| core count         = 1024
 +
| thread count       =  
 +
| max cpus            =
 +
| max memory          =
 +
| max memory addr    =
 +
 
 +
| electrical          = Yes
 +
| power               = 70 W
 +
| v core             = 0.9 V
 +
| v core tolerance    =
 +
| v io                =
 +
| v io tolerance      =
 +
| sdp                =
 +
| tdp                =
 +
| ctdp down          =
 +
| ctdp down frequency =
 +
| ctdp up            =
 +
| ctdp up frequency  =
 +
| temp min            =
 +
| temp max            =
 +
| tjunc min          = <!-- °C -->
 +
| tjunc max          =
 +
| tcase min          =
 +
| tcase max          =
 +
| tstorage min        =
 +
| tstorage max        =  
 +
 
 +
| packaging           = Yes
 +
| package 0           = fcBGA-2397
 +
| package 0 type     = fcBGA
 +
| package 0 pins     = 2,397
 +
| package 0 pitch     = 1 mm
 +
| package 0 width     = 50 mm
 +
| package 0 length   = 50 mm
 +
| package 0 height    =
 +
| socket 0           = BGA-2397
 +
| socket 0 type       = BGA
 
}}
 
}}
 +
'''PEZY-SCnp''' (SC - '''Super Computer'''; np - '''New Package''') is a revised version of the {{pezy|PEZY-SC}} model by [[PEZY]] introduced in may of 2016. The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. The PEZY-SCnp is said to deliver 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. As with the PEZ-SC, the SCnp is also manufactured on TSMC's 28HPC+ ([[28 nm process]]).
  
 
== Architecture ==
 
== Architecture ==
−
{{further|pezy/pezy-scx/pezy-sc#Architecture|pezy/pezy-scx#Architecture|l1=PEZY-SC § Architecture|l2=PEZY-SCx § Architecture}}
+
{{main|pezy/pezy-sc#Architecture|l1=PEZY-SC §Architecture}}
 
The PEZY-SCnp's architecture is identical to the {{pezy|PEZY-SC}}.
 
The PEZY-SCnp's architecture is identical to the {{pezy|PEZY-SC}}.
  
 
== Cache ==
 
== Cache ==
−
PEZY-SC's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared).
+
PEZY-SC's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of 32KB (2x) and 64KB L2$ (shared).
−
{{cache size
+
{{cache info
−
|l1 cache=64 KiB
+
|l1i cache=2 MB
−
|l1i cache=32 KiB
+
|l1i break=1024x2 KB
−
|l1i break=2x16 KiB
+
|l1i desc=
−
|l1d cache=32 KiB
+
|l1i extra=(per processor element)
−
|l1d break=2x16 KiB
+
|l1d cache=1 MB
−
|l2 cache=64 KiB
+
|l1d break=512x2 KB
−
|l2 break=1x64 KiB
+
|l1d desc=
 +
|l1d extra=(per 2 processor elements)
 +
|l2 cache=4 MB
 +
|l2 break=4x2 MB
 +
|l2 desc=
 +
|l2 extra=(per city)
 +
|l3 cache=8 MB
 +
|l3 break=4x2 MB
 +
|l3 desc=
 +
|l3 extra=(per prefecture)
 
}}
 
}}
−
 
−
The chip integrates a multi-level cache hierarchy:
 
−
{{cache size
 
−
|l1 cache=3 MiB
 
−
|l1i cache=2 MiB
 
−
|l1i break=1024x2 KiB
 
−
|l1i desc=per processor element
 
−
|l1d cache=1 MiB
 
−
|l1d break=512x2 KiB
 
−
|l1d desc=per 2 processor elements
 
−
|l1d policy=
 
−
|l2 cache=4 MiB
 
−
|l2 break=4x2 MiB
 
−
|l2 desc=per city
 
−
|l2 policy=write-back
 
−
|l3 cache=8 MiB
 
−
|l3 break=4x2 MiB
 
−
|l3 desc=per prefecture
 
−
|l3 policy=
 
−
}}
 
−
 
−
Additionally, there is another 16 MiB of scratch-pad memory consisting of 16 KiB per PE.
 
  
 
== Memory controller ==
 
== Memory controller ==
−
{{memory controller
+
{{integrated memory controller
−
|type=DDR4-2133
+
| type               = DDR4-1866
−
|ecc=Yes
+
| controllers       = 1
−
|controllers=8
+
| channels           = 8
−
|channels=8
+
| ecc support        = <!-- ?? -->
−
|width=64 bit
+
| bandwidth schan   = 14,933 MB/s
−
|max bandwidth=127.156 GiB/s
+
| bandwidth dchan   = 29,866 MB/s
−
|bandwidth schan=15.89 GiB/s
+
| bandwidth qchan   = 59,732 MB/s
−
|bandwidth dchan=31.79 GiB/s
+
| bandwidth ochan    = 119,464 MB/s
−
|bandwidth qchan=63.58 GiB/
+
| max memory        =  
−
|bandwidth hchan=95.37 GiB/s
 
−
|bandwidth ochan=127.156 GiB/s
 
 
}}
 
}}
  
 
== Expansions ==
 
== Expansions ==
−
{{expansions main
+
{{mpu expansions
−
|
+
| pcie revision      = 3.0
−
{{expansions entry
+
| pcie lanes        = 8
−
|type=PCIe
+
| pcie config        =  
−
|pcie revision=3.0
+
| pcie config 1      =  
−
|pcie lanes=32
+
| pcie config 2      =  
−
|pcie config=4x8
+
| usb revision      =
−
}}
+
| usb revision 2    =
 +
| usb ports          =
 +
| sata revision      =
 +
| sata ports        =
 +
| integrated lan    =
 +
| uart              = Yes
 +
| gp io              = Yes
 
}}
 
}}

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Facts about "PEZY-SCnp - PEZY"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
PEZY-SCnp - PEZY#pcie + and PEZY-SCnp - PEZY#package +
base frequency766.66 MHz (0.767 GHz, 766,660 kHz) +
core count1,024 +
core voltage0.95 V (9.5 dV, 95 cV, 950 mV) +
designerPEZY +
familyPEZY-SCx +
first announcedMay 6, 2016 +
first launchedMay 6, 2016 +
full page namepezy/pezy-scx/pezy-scnp +
has ecc memory supporttrue +
instance ofmicroprocessor +
l1$ size64 KiB (65,536 B, 0.0625 MiB) + and 3,072 KiB (3,145,728 B, 3 MiB) +
l1d$ descriptionper 2 processor elements +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) + and 1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ descriptionper processor element +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) + and 2,048 KiB (2,097,152 B, 2 MiB) +
l2$ descriptionper city +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + and 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
l3$ descriptionper prefecture +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldateMay 6, 2016 +
main imageFile:pezy-scnp (front).png +
manufacturerTSMC +
market segmentSupercomputer +
max memory bandwidth127.156 GiB/s (130,207.744 MiB/s, 136.533 GB/s, 136,532.715 MB/s, 0.124 TiB/s, 0.137 TB/s) +
max memory channels8 +
model numberPEZY-SCnp +
namePEZY-SCnp +
packageFCBGA-2397 +
peak flops (double-precision)1,570,133,331,968 FLOPS (1,570,133,331.968 KFLOPS, 1,570,133.332 MFLOPS, 1,570.133 GFLOPS, 1.57 TFLOPS, 0.00157 PFLOPS, 1.570133e-6 EFLOPS, 1.570133e-9 ZFLOPS) +
peak flops (single-precision)3,140,266,663,936 FLOPS (3,140,266,663.936 KFLOPS, 3,140,266.664 MFLOPS, 3,140.267 GFLOPS, 3.14 TFLOPS, 0.00314 PFLOPS, 3.140267e-6 EFLOPS, 3.140267e-9 ZFLOPS) +
power dissipation100 W (100,000 mW, 0.134 hp, 0.1 kW) +
power dissipation (average)70 W (70,000 mW, 0.0939 hp, 0.07 kW) +
process28 nm (0.028 μm, 2.8e-5 mm) +
supported memory typeDDR4-2133 +
technologyCMOS +
thread count8,192 +