From WikiChip
Editing nervana/microarchitectures/lake crest
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 55: | Line 55: | ||
* Rao, N. (2016, November). ''Pathfinding and Hardware Deep Dive''. 2016 AI Day, San Francisco. | * Rao, N. (2016, November). ''Pathfinding and Hardware Deep Dive''. 2016 AI Day, San Francisco. | ||
* Rao, N. (2018, May). ''Keynote presentation''. 2018 AI DevCon, San Francisco. | * Rao, N. (2018, May). ''Keynote presentation''. 2018 AI DevCon, San Francisco. | ||
+ | ggggg |
Facts about "Lake Crest - Microarchitectures - Intel Nervana"
codename | Lake Crest + |
designer | Nervana + |
first launched | November 17, 2016 + |
full page name | nervana/microarchitectures/lake crest + |
instance of | microarchitecture + |
manufacturer | TSMC + |
name | Lake Crest + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |