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| | {{microsoft title|Scorpio Engine}} | | {{microsoft title|Scorpio Engine}} |
| − | {{chip | + | {{mpu |
| | |name=Scorpio Engine | | |name=Scorpio Engine |
| | |image=scorpio engine (front).png | | |image=scorpio engine (front).png |
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| | |first launched=November 7, 2017 | | |first launched=November 7, 2017 |
| | |frequency=2,300 MHz | | |frequency=2,300 MHz |
| | + | |clock multiplier=23 |
| | |isa=x86-64 | | |isa=x86-64 |
| | |isa family=x86 | | |isa family=x86 |
| | |microarch=Enhanced Jaguar | | |microarch=Enhanced Jaguar |
| − | |microarch 2=Polaris | + | |microarch 2=Arctic Islands |
| | |core name=Enhanced Jaguar | | |core name=Enhanced Jaguar |
| | |process=16 nm | | |process=16 nm |
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| | |technology=CMOS | | |technology=CMOS |
| | |die area=359 mm² | | |die area=359 mm² |
| − | |mcp=No
| |
| | |word size=64 bit | | |word size=64 bit |
| | |core count=8 | | |core count=8 |
| | |thread count=8 | | |thread count=8 |
| | |max cpus=1 | | |max cpus=1 |
| − | |max memory=24 GiB | + | |max memory=12 GiB |
| − | |package name=amd/packages/bga-2409
| |
| | }} | | }} |
| | '''Scorpio Engine''' is a {{arch|64}} [[octa-core]] [[x86]] SoC designed by [[AMD]] and [[Microsoft]] for their ''Xbox One X''. The chip features eight {{amd|Enhanced Jaguar|l=arch}} cores operating at 2.3 GHz and a custom {{amd|Arctic Islands|l=arch}}-based GPU operating at 1.172 GHz. Fabricated on [[TSMC]]'s [[16 nm process|16FF+]], this chip supports 12 (24 for Dev) GiB of 12-channel GDDR5-6800 memory. | | '''Scorpio Engine''' is a {{arch|64}} [[octa-core]] [[x86]] SoC designed by [[AMD]] and [[Microsoft]] for their ''Xbox One X''. The chip features eight {{amd|Enhanced Jaguar|l=arch}} cores operating at 2.3 GHz and a custom {{amd|Arctic Islands|l=arch}}-based GPU operating at 1.172 GHz. Fabricated on [[TSMC]]'s [[16 nm process|16FF+]], this chip supports 12 (24 for Dev) GiB of 12-channel GDDR5-6800 memory. |
| − |
| |
| − | == Overview ==
| |
| − | Like the ''PlayStation 4'' and the ''Xbox One'', the ''Xbox One X'' is also powered by a chip based on [[AMD]]'s architectures. The ''Scorpio Engine'' most important goal was achieving true [[4K]] gaming performance according to John Sell, a Distinguished Engineer at Microsoft who presented the chip at [[Hot Chips]] 29. Fabricated on [[TSMC]]'s [[16 nm process]], the chip contains 7 billion [[transistors]] on a 359 mm² [[die]], similar in amount to [[Nvidia]]'s {{nvidia|GTX 1080}} and almost the same size as the original Xbox One SoC (which was 363 mm² on a [[28 nm process]]).
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| − |
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| − | Like the original Xbox One SoC, the chip feature eight Jaguar cores. The cores have been {{amd|Enhanced Jaguar|lightly enhanced|l=arch}} and operate at a higher frequency of 2.3 GHz, but are otherwise mostly identical. It's worth pointing out that [[AMD]] has not commercialized a 16 nm Jaguar processor outside of this chip.
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| − |
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| − |
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| − | :[[File:scorpio engine block diagram.png|750px]]
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| | | | |
| | == Cache == | | == Cache == |
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| | | | |
| | == Memory controller == | | == Memory controller == |
| − | The memory architecture of the Scorpio Engine is very different from the previous generational chip. The entire memory subsystem was redesigned to address the major deficiencies in prior chips. In previous chip, Microsoft chose to go with 8 GiB of quad-channel [[DDR3]] on-board operating at 2133 MT/s for a total system memory [[bandwidth]] of 63.58 GiB/s. That was fairly low by any standard; at the time the PS4 SoC had a peak memory bandwidth of 163.9 GiB/s. In an attempt to mitigate the lack of bandwidth, the chip incorporated 32 MiB of [[eSRAM]] with a bus of 1,024-bit in each direction for a total bandwidth of 190 GiB/s. While this reduced the cost of memory considerably, it increased the cost in terms of die area (which would be roughly 1.6B transistors). Additionally, this architecture also made the programming model more complicated to work with.
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| − |
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| − | The Scorpio Engine made a 180-degree turn vs previous chip architecture-wise. The entire memory subsystem has been re-designed with GDDR5 and high bandwidth in mind. The previous 32 MiB of [[eSRAM]] has been eliminated. Instead, Scorpio has a maximum bandwidth of 304 GiB/s through a 384-bit wide [[DRAM]] interface with an effective transfer of 6800 MT/s. The bandwidth increase has effectively reached the level of a discrete graphics card and almost 1.5x the bandwidth of the PS4 Pro (which is 203 GiB/s).
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| − |
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| − | Console systems will come with 12 x32 [[GDDR]] chips for a total of 12 [[GiB]] while the development system will come with x16 chips for a total capacity of 24 GiB. Scorpio has 12 [[DRAM controllers]] for each of the 12 channels. It's worth noting that in order to maintain backwards compatibility with the Xbox One software, the [[CPU]] and [[GPU]] accesses the memory separately. The exact details of how the CPU accesses the memory has not been detailed. As with the previous generation, a bidirectional bus sits between the [[memory controllers]] and the CPUs and GPU. The bus maintains [[coherency]] between the CPU cores and the GPU. For the GPU, each of the 12 [[memory channel|channels]] is a 256-bit directional bus for a total bus width of 3,072-bit. The 12 channels allow the system to lower the granularity of memory accesses while the wide bus allows the system to take full advantage of the available bandwidth.
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| − |
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| | {{memory controller | | {{memory controller |
| | |type=GDDR5-6800 | | |type=GDDR5-6800 |
| − | |ecc=No
| + | |max mem=12 GiB |
| − | |max mem=24 GiB | |
| | |controllers=12 | | |controllers=12 |
| | |channels=12 | | |channels=12 |
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| | | | |
| | == Graphics == | | == Graphics == |
| − | {{further|amd/microarchitectures/arctic islands|l1=Arctic Islands microarchitecture}} | + | {{main|amd/microarchitectures/arctic islands|l1=Arctic Islands microarchitecture}} |
| − | {| class="wikitable" style="float: right;"
| + | Scorpio Engine features a 40 Radeon compute units (CU) operating at 1,172 MHz each capable of 128 FLOP/cycle for a total of 6.00064 TFLOPS raw peak performance. The GPU is capable of 4.688 Giga primitives/second and 187.5 G bilinear texels/second. |
| | + | |
| | + | <table class="wikitable"> |
| | + | <tr><th colspan="2">Scorpio Engine GPU</th></tr> |
| | + | <tr><th>Unified shaders</th><td>2560 (64 × 40 CUs)</td></tr> |
| | + | <tr><th>[[raster operation units|ROPs]]</th><td>32</td></tr> |
| | + | <tr><th>[[texture mapping units |TMUs]]</th><td>160</td></tr> |
| | + | <tr><th>Peak Performance</th><td> ~6 TFLOPS (6,000,640,000,000 [[FLOPS]])</td></tr> |
| | + | </table> |
| | + | |
| | + | {| class="wikitable" |
| | ! colspan="3" | Hardware Accelerated Video Capabilities | | ! colspan="3" | Hardware Accelerated Video Capabilities |
| | |- | | |- |
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| | | [[VP9]] || {{tchk|yes|4K @ 60 Hz}} || {{tchk|no}} | | | [[VP9]] || {{tchk|yes|4K @ 60 Hz}} || {{tchk|no}} |
| | |} | | |} |
| − | Scorpio Engine feature 40 or 44 Compute Units (CUs) for the consumer console and dev kit respectively based on {{amd|Arctic Islands|l=arch}} (Similar to Polaris, Radeon RX 4xx). This is triple the amount over the original Xbox One SoC. The Compute Units operate at 1,172 MHz, each with 64 32-bit [[floating point]] [[multiply-accumulate]] units. At 1.172 GHz with 128 FLOP/cycle this chip can deliver 6.00064 [[TFLOPS]] raw peak performance - over four times previous chips (which were 1.3 and 1.4 TFLOPS). The dev kit can deliver a reported 6.6 TFLOPS with its four additional CUs. The performance of texture processing has also been increased to 187.5 G bilinear [[texels]]/second. Additionally, in each of the four [[shader]] arrays, there is one geometry engine for the purpose of doing fixed geometry processing, this is twice previous chip which is capable of 4.688 Giga primitives/second.
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| − |
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| − | Similar to previous chips, Scorpio has 2 command processors (i.e., microcontrollers) that handle graphic and compute tasks however they are said to handle more parallel compute tasks than previous chip in order to increase performance. The number of ACEs (Asynchronous Compute Engine) on Scorpio has doubled to 4 in order to increase the [[parallelism]] possible. It's worth pointing out that since the Scorpio Engine is based on {{amd|Arctic Islands|l=arch}}, there are also two additional schedulers.
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| − |
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| − | [[File:scorpio engine rb-mem subsys.svg|right|400px]]
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| − | <table class="wikitable">
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| − | <tr><th colspan="2">Scorpio Engine GPU</th></tr>
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| − | <tr><th>Unified shaders</th><td>2560 (64 × 40 CUs), (dev kit) 2816 (64 × 44 CUs)</td></tr>
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| − | <tr><th>[[raster operation units|ROPs]]</th><td>32</td></tr>
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| − | <tr><th>[[texture mapping units |TMUs]]</th><td>160</td></tr>
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| − | <tr><th>Peak Performance</th><td> ~6 TFLOPS (6,000,640,000,000 [[FLOPS]]), (dev kit) ~6.6 TFLOPS</td></tr>
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| − | </table>
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| − |
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| − | === RBs and Memory Subsystem ===
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| − | The render back-end has also been enhanced. The render back-end consist of eight ''Render Boxes'' (RB) color/depth engines, each with 256 KiB graphics L2 cache for a total of 2 MiB. Each pair of Render Boxes is wired to one ''Memory Controller Cluster'' (MCC). Each MMC consists of two dedicated memory controllers and two more that are shared between two pairs of MCCs. In total there are four clusters with each having two dedicated controllers and two more pair (4 controllers) of channels shared between a pair of MCCs for a total of 12 channels.
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| − |
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| − | {{clear}}
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| | | | |
| | == Display == | | == Display == |
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| | | | |
| | == Utilizing devices == | | == Utilizing devices == |
| − | The Scorpio Engine is used solely in the [[used by::Xbox One X]] and its dev kit.
| + | * [[used by::Xbox One X]] |
| | + | |
| | + | {{expand list}} |
| | | | |
| | == Die == | | == Die == |
| | + | {{see also|amd/microarchitectures/scorpio_engine#Die|l1=Scorpio Engine microarchitecture § Die}} |
| | * TSMC's [[16 nm process|16 nm FF+ process]] | | * TSMC's [[16 nm process|16 nm FF+ process]] |
| | * 7,000,000,000 transistors | | * 7,000,000,000 transistors |
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| | | | |
| | : [[File:scorpio engine die shot (annotated).png|750px]] | | : [[File:scorpio engine die shot (annotated).png|750px]] |
| − |
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| − | === Yield & redundancy ===
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| − | In normal microprocessors such as typical [[CPU]]s and [[GPU]]s, when a core in the case of a CPU or a shader unit in the case of a GPU has a defect, it's common for manufacturers to disable those affected cores/shaders (typically in a symmetrical way) and [[binning|sell those chips as lower end models]]. Since the Scorpio Engine is only found in the single-specification ''Xbox One X'' machine and its dev kit, [[binning]] is not as flexible. In an attempt to improve yield for the consumer models the Scorpio Engine actually incorporates 11 Compute Units (CUs) in each shader array for redundancy, 10 of them are operational while an 11th one is used as a spare. With 4 shader arrays, there are 4 spares and 40 enabled CUs. If one or a few compute units are faulty but the rest of the chip is fully functional, the spare CUs can be enabled to compensate for this. Fully unlocked Scorpio Engines are incorporated in the dev kits, though in lower volume than the consumer models.
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| − |
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| − | == Package ==
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| − | [[Category:all ic packages]]{{#set:package=BGA-2409|package type=FC-OBGA}}
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| − | * Lidless [[ball grid array]] package with stiffener frame, [[package length::50 mm]] × [[package width::50 mm]]
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| − | ** [[package contacts::2409]] balls, [[package pitch::0.8 mm]] minimum non-uniform pitch
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| − | ** 12 layer (5-2-5)<!--ISSCC2021-XSX Paternoster--> organic substrate, [[flip chip]] die attachment
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| − |
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| − | * 12 × 32 bit GDDR5 SDRAM interface
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| − | ** 850 MHz, 6800 MT/s, 326.4 GB/s total raw bandwidth
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| − | ** XBox consumer model: 1 × DRAM Down per channel, 256M×32 = 1 GiB
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| − |
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| − | * 8-lane PCIe Gen 1, 2, 3 (8 GT/s) interface
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| − | ** Up to 5 ports configurable x4, x2, x1 with power-of-two alignment
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| − | ** x4 General Purpose Ports (x4 SSD M.2)
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| − | ** x4 Unified Media Interface (x2 South Bridge, x1 Ethernet, x1 spare)
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| − |
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| − | * Display Port 0
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| − | ** {{abbr|DP}} 1.2a with 2-stream {{abbr|MST}}, {{abbr|HDMI}} 2.0b, {{abbr|HDCP}} 2.2
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| − | ** Resolution up to 4096 × 2160, 60 Hz
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| − |
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| − | * Display Port 1
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| − | ** DP 1.2a input (lanes 0-1 used for HDMI passthrough via HDMI-DP converter in SB)
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| − |
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| − | * Low speed interfaces:
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| − | ** {{abbr|S/PDIF}} output ({{wp|TOSLINK}} connector)
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| − | ** {{abbr|GPIO}}
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| − | ** Sideband Interface ({{abbr|SB-TSI}})
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| − | ** Serial VID Interface ({{amd|SVI2}})
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| − | ** {{abbr|JTAG}}
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| − |
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| − | === Package Diagram ===
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| − | [[File:BGA-2409 diag.svg]]
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| − |
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| − | All dimensions in millimeters.
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| − |
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| − | [[:File:BGA-2409 pn.svg|Ball numbers]]
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| − |
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| − | === Pin Map ===
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| − | [[File:BGA-2409 pinmap.svg|800px]]
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| − |
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| − | Pinout, top view. Click for a larger image and other views.
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| − |
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| − | [[:File:BGA-2409 pinout.ods|Spreadsheet]]
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| − |
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| − | ==== Pin Description ====
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| − | Signals with names ending in _N are active low.
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| − |
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| − | {| class="wikitable sortable"
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| − | ! Signal !! Description
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| − | |-
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| − | | (A0-F0/A1-F1)_ADBI || DRAM Channel A-F, Subchannel 0-1 Address Bus Inversion
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| − | |-
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| − | | (A0-F0/A1-F1)_CAS_N || DRAM Column Address Strobe
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| − | |-
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| − | | (A0-F0/A1-F1)_CKE0 || DRAM Clock Enable for Address/Command Bus
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| − | |-
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| − | | (A0-F0/A1-F1)_CLK0_P/N || DRAM Differential Clock for Address/Command Bus
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| − | |-
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| − | | (A0-F0/A1-F1)_CS0_N || DRAM Chip Select
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| − | |-
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| − | | (A0-F0/A1-F1)_DDBI_(0-3) || DRAM Data Bus Inversion, byte 0-3
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| − | |-
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| − | | (A0-F0/A1-F1)_DQ[31:0] || DRAM Data Bus
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| − | |-
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| − | | A-F_DRAM_RESET || DRAM Reset
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| − | |-
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| − | | (A0-F0/A1-F1)_EDC_(0-3) || DRAM Error Detection and Correction, Data Bus byte 0-3
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| − | |-
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| − | | (A0-F0/A1-F1)_MA_A[7:0] || DRAM Column/Row Address
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| − | |-
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| − | | (A0-F0/A1-F1)_MA_A12 || DRAM Column/Row Address 12
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| − | |-
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| − | | A-F_MEM_CAL ||
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| − | |-
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| − | | A-F_MEM_VREFDQ || DRAM Input Reference for Data Bus
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| − | |-
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| − | | (A0-F0/A1-F1)_RAS_N || DRAM Row Address Strobe
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| − | |-
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| − | | (A0-F0/A1-F1)_WCK0/WCK1_P/N || DRAM Differential Forward Clock for Data Bus byte 0-1/2-3
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| − | |-
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| − | | (A0-F0/A1-F1)_WE_N || DRAM Write Enable
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| − | |-
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| − | | P_GPP_RX(0-3)_P/N || PCIe {{abbr|GPP}} Receive Data Differential Pairs
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| − | |-
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| − | | P_GPP_TX(0-3)_P/N || PCIe GPP Transmit Data Differential Pairs
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| − | |-
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| − | | P_UMI_RX(0-3)_P/N || PCIe {{abbr|UMI}} Receive Data Differential Pairs
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| − | |-
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| − | | P_UMI_TX(0-3)_P/N || PCIe UMI Transmit Data Differential Pairs
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| − | |-
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| − | | DP0_TX(0-3)_P/N || {{wp|DisplayPort}} 0 Main Link Differential Transmitter Lane 0-3 or {{abbr|HDMI}} Channel 2, 1, 0, Clock
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| − | |-
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| − | | DP1_RX(0-3)_P/N || DisplayPort 1 Differential Receiver (HDMI passthrough)
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| − | |-
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| − | | DP0/DP1_AUX_P/N || DisplayPort 0-1 Auxiliary Channel or HDMI DDC Clock, Data
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| − | |-
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| − | | DP0/DP1_HPD || DisplayPort 0-1 Hot Plug Detect input
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| − | |-
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| − | | DP_AUX_ZVSS ||
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| − | |-
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| − | | SPDIF_OUT || {{abbr|S/PDIF}} Output ({{wp|TOSLINK}} connector)
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| − | |-
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| − | | 1P8V_GPIO(0-9) || {{abbr|GPIO}}
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| − | |-
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| − | | 3P3V_GPIO(0-3) ||
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| − | |-
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| − | | AV_CLKIN_P/N ||
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| − | |-
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| − | | CLKIN_P/N ||
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| − | |-
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| − | | CLKIN_NB_P/N ||
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| − | |-
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| − | | DISP_CLKIN_P/N ||
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| − | |-
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| − | | X32K_X1/X2 || 32768 Hz Real Time Clock XTAL
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| − | |-
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| − | | RTCCLK || 32768 Hz Real Time Clock
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| − | |-
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| − | | PSEN ||
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| − | |-
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| − | | PWROK || Power OK input; Indicates that all voltage planes and free-running clocks are within specification
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| − | |-
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| − | | RESET_N || Processor Reset
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| − | |-
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| − | | ALERT_N || {{abbr|SB-TSI}} Interrupt
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| − | |-
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| − | | SIC || Sideband Interface Clock ({{abbr|SB-TSI}})
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| − | |-
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| − | | SID || Sideband Interface Data
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| − | |-
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| − | | THERMDA || Thermal Diode Anode
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| − | |-
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| − | | THERMDC || Thermal Diode Cathode
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| − | |-
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| − | | THERMTRIP_N || {{x86|thermal protection|Temperature Trip}} Output
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| − | |-
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| − | | DBREQ_N || Debug Request input to JTAG controller
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| − | |-
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| − | | DBRDY || Debug Ready
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| − | |-
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| − | | TCK || {{abbr|JTAG}} Clock
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| − | |-
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| − | | TDI || JTAG Data Input
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| − | |-
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| − | | TDO || JTAG Data Output
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| − | |-
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| − | | TMS || JTAG Mode Select
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| − | |-
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| − | | TRST_N || JTAG Reset
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| − | |-
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| − | | BP_(0-3) || Break Point Indicator
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| − | |-
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| − | | ANALOGOUT ||
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| − | |-
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| − | | ANATSTIN_P/N ||
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| − | |-
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| − | | ANATSTOUT_P/N ||
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| − | |-
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| − | | {{abbr|ATE}}_TSTCLK_EN ||
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| − | |-
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| − | | BYPASSCLK_P/N ||
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| − | |-
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| − | | DIECRACKMON || Die edge crack monitoring
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| − | |-
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| − | | PLLTEST0 ||
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| − | |-
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| − | | PLLTEST1 ||
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| − | |-
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| − | | VDD_BURN_1/2 ||
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| − | |-
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| − | | SVC || Serial VID Clock ({{amd|SVI2}})
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| − | |-
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| − | | SVD || Serial VID Data
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| − | |-
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| − | | SVT || Serial VID Telemetry
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| − | |-
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| − | | VDD_CORE || Core Power Supply
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| − | |-
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| − | | VDD_CORE_PROBE ||
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| − | |-
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| − | | VSS_CORE_PROBE ||
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| − | |-
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| − | | VDD_CORE_SENSE ||
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| − | |-
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| − | | VSS_CORE_SENSE ||
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| − | |-
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| − | | VDD_NB || North Bridge Power Supply
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| − | |-
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| − | | VDD_NB_SENSE ||
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| − | |-
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| − | | VSS_NB_SENSE ||
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| − | |-
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| − | | VDD_GFX || GPU Power Supply
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| − | |-
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| − | | VDD_GFX_PROBE ||
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| − | |-
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| − | | VSS_GFX_PROBE ||
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| − | |-
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| − | | VDD_GFX_SENSE ||
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| − | |-
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| − | | VSS_GFX_SENSE ||
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| − | |-
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| − | | VDD_MEM ||
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| − | |-
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| − | | VDD_MEM_SENSE ||
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| − | |-
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| − | | VSS_MEM_SENSE ||
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| − | |-
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| − | | VDD_MEMP ||
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| − | |-
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| − | | VDD_MEMP_PROBE ||
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| − | |-
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| − | | VSS_MEMP_PROBE ||
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| − | |-
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| − | | VDD_MEMP_SENSE ||
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| − | |-
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| − | | VDD_095 || 0.95 V Supply Voltage
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| − | |-
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| − | | VDD_095_SENSE ||
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| − | |-
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| − | | VSS_095_SENSE ||
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| − | |-
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| − | | VDD_18 || 1.8 V Supply Voltage
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| − | |-
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| − | | VDD_33 || 3.3 V Supply Voltage
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| − | |-
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| − | | VDD_FUSE ||
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| − | |-
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| − | | VDDBT_RTC_G || Integrated Real Time Clock battery power supply
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| − | |-
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| − | | VSS || Ground
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| − | |-
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| − | | A0_BYPASS ||
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| − | |-
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| − | | DLY_PSP_RESET ||
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| − | |-
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| − | | P_ZCAL_VDD_095 ||
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| − | |-
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| − | | P_ZCAL_VSS ||
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| − | |-
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| − | | SPARE ||
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| − | |-
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| − | | TMON_CAL0 ||
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| − | |-
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| − | | TMON_CAL1 ||
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| − | |}
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| − |
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| − | == References ==
| |
| − | * {{cite presentation|presenters=Sell, John|title=The Xbox One X Scorpio Engine|url=https://hc29.hotchips.org|date=2017-08-21|conference=Hot Chips 29}}
| |
| − | * {{cite presentation|presenters=Sell, John;O'Connor, Patrick|title=XBOX One Silicon|url=https://hc25.hotchips.org|date=2013-08-26|conference=Hot Chips 25}}
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| − | * {{cite presentation|presenters=Paternoster, Paul|authors=Maki, Andy;Hernandez, Andres;Grossman, Mark;Lau, Michael;Sutherland, David;Mathad, Aditya|title=XBOX SERIES X SoC – A Next Generation Gaming Console|slides=File:ISSCC2021 3.1 XSX Paternoster slides.pdf|date=2021-02-15|conference=IEEE ISSCC 2021|session=3.1}}
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