Revision as of 04:02, 3 December 2016

Template:mpu Helio X10 (MT6795) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and introduced in early-2014. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 28 nm process, operates at up to 2 GHz and supports dual-channel LPDDR3-933. This chip incorporates the PowerVR G6200 IGP operating at 700 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 4.

This SoC is made of 2 clusters of 4-core each (Cortex-A53) linked together via a CCI-400, a NEON engine, and Cortex-R4 core for the second MCU subsystem.

Cache

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 512 KiB 524,288 B 0.5 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 2-way set associative   L1D$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 4-way set associative   L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     2x1 MiB 16-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-933 Supports ECC No Max Mem 4 GiB Controllers 1 Channels 2 Max Bandwidth 13.9 GiB/s 14,233.6 MiB/s 14.925 GB/s 14,925.011 MB/s 0.0136 TiB/s 0.0149 TB/s Bandwidth Single 6.95 GiB/s Double 13.9 GiB/s

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU PowerVR G6200 Designer Imagination Technologies Frequency 550 MHz 0.55 GHz 550,000 KHz Standards Direct3D 10.0 OpenGL 3.2 OpenCL 1.2 Vulkan 1.0