Difference between revisions of "intel/xeon gold/6148"

Revision as of 13:38, 26 May 2017

Template:mpu Xeon Gold 6148 is a 64-bit x86 high-performance server icosa-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 6148 operates at 2.4 GHz.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

1.25 MiB

1,280 KiB
1,310,720 B

L1I$	640 KiB 655,360 B 0.625 MiB	20x32 KiB	8-way set associative
L1D$	640 KiB 655,360 B 0.625 MiB	20x32 KiB	8-way set associative	write-back

L2$

20 MiB

20,480 KiB
20,971,520 B
0.0195 GiB

		20x1 MiB	16-way set associative	write-back

L3$

27.5 MiB

28,160 KiB
28,835,840 B
0.0269 GiB

		20x1.375 MiB	16-way set associative	write-back

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2666
Supports ECC	Yes
Controllers	1
Channels	6
Max Bandwidth	119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s
Bandwidth	Single 19.89 GiB/s Double 39.72 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s

@@ Line 126: / Line 126: @@
 |l2 cache=20 MiB
 |l2 break=20x1 MiB
-|l2 desc=4-way set associative
+|l2 desc=16-way set associative
 |l2 policy=write-back
 |l3 cache=27.5 MiB

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 6148 - Intel#io +, Xeon Gold 6148 - Intel +, Xeon Gold 6148 - Intel +, Xeon Gold 6148 - Intel +, Xeon Gold 6148 - Intel +, Xeon Gold 6148 - Intel +, Xeon Gold 6148 - Intel +, Xeon Gold 6148 - Intel +, Xeon Gold 6148 - Intel +, Xeon Gold 6148 - Intel + and Xeon Gold 6148 - Intel +
base frequency	2,400 MHz (2.4 GHz, 2,400,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	24 +
core count	20 +
core family	6 +
core name	Skylake SP +
core stepping	H0 +
cpuid	0x50654 +
designer	Intel +
family	Xeon Gold +
first announced	April 25, 2017 +
first launched	July 11, 2017 +
full page name	intel/xeon gold/6148 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	1,280 KiB (1,310,720 B, 1.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	640 KiB (655,360 B, 0.625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	640 KiB (655,360 B, 0.625 MiB) +
l2$ description	16-way set associative +
l2$ size	20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +
l3$ description	11-way set associative +
l3$ size	27.5 MiB (28,160 KiB, 28,835,840 B, 0.0269 GiB) +
ldate	July 11, 2017 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	359.15 K (86 °C, 186.8 °F, 646.47 °R) +
max cpu count	4 +
max dts temperature	95 °C +
max memory	786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
microarchitecture	Skylake (server) +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature	0 °C +
model number	6148 +
name	Xeon Gold 6148 +
package	FCLGA-3647 +
part number	BX806736148 + and CD8067303406200 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 3,072.00 (€ 2,764.80, £ 2,488.32, ¥ 317,429.76) +
s-spec	SR3B6 +
s-spec (qs)	QMS1 +
series	6100 +
smp interconnect	UPI +
smp interconnect links	3 +
smp interconnect rate	10.4 GT/s +
smp max ways	4 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2666 +
tdp	150 W (150,000 mW, 0.201 hp, 0.15 kW) +
technology	CMOS +
thread count	40 +
turbo frequency (1 core)	3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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Revision as of 13:38, 26 May 2017

Cache

Memory controller