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Difference between revisions of "intel/xeon gold/6146"
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'''Xeon Gold 6146''' is a {{arch|64}} [[dodeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6146, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3.2 GHz with a TDP of 165 W and a {{intel|turbo boost}} frequency of up to 4.2 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
 
'''Xeon Gold 6146''' is a {{arch|64}} [[dodeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6146, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3.2 GHz with a TDP of 165 W and a {{intel|turbo boost}} frequency of up to 4.2 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
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== Cache ==
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{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
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{{cache size
 +
|l1 cache=768 KiB
 +
|l1i cache=384 KiB
 +
|l1i break=12x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=384 KiB
 +
|l1d break=12x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=12 MiB
 +
|l2 break=12x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=16.5 MiB
 +
|l3 break=12x1.375 MiB
 +
|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}

Revision as of 00:58, 12 July 2017

Template:mpu Xeon Gold 6146 is a 64-bit dodeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6146, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3.2 GHz with a TDP of 165 W and a turbo boost frequency of up to 4.2 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
0.75 MiB
786,432 B
7.324219e-4 GiB
L1I$384 KiB
0.375 MiB
393,216 B
3.662109e-4 GiB
12x32 KiB8-way set associative 
L1D$384 KiB
0.375 MiB
393,216 B
3.662109e-4 GiB
12x32 KiB8-way set associativewrite-back

L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  12x1 MiB16-way set associativewrite-back

L3$16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
  12x1.375 MiB11-way set associativewrite-back
l1$ size0.75 MiB (768 KiB, 786,432 B, 7.324219e-4 GiB) +
l1d$ description8-way set associative +
l1d$ size0.375 MiB (384 KiB, 393,216 B, 3.662109e-4 GiB) +
l1i$ description8-way set associative +
l1i$ size0.375 MiB (384 KiB, 393,216 B, 3.662109e-4 GiB) +
l2$ description16-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description11-way set associative +
l3$ size16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +