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The '''Xeon E5-2620 v4''' is a {{arch|64}} [[octa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for standard 2S environments (1U square form factor). Operating at 2.1 GHz with a {{intel|turbo boost}} frequency of 3 GHz for a single active core, this MPU has a TDP of 85 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 
The '''Xeon E5-2620 v4''' is a {{arch|64}} [[octa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for standard 2S environments (1U square form factor). Operating at 2.1 GHz with a {{intel|turbo boost}} frequency of 3 GHz for a single active core, this MPU has a TDP of 85 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
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== Cache ==
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{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
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{{cache info
 +
|l1i cache=256 KiB
 +
|l1i break=8x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1i extra=(per core, write-back)
 +
|l1d cache=256 KiB
 +
|l1d break=8x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d extra=(per core, write-back)
 +
|l2 cache=4 MiB
 +
|l2 break=16x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 extra=(per core, write-back)
 +
|l3 cache=40 MiB
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|l3 break=16x2.5 MiB
 +
|l3 desc=20-way set associative
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|l3 extra=(shared, per core, write-back)
 +
}}

Revision as of 04:27, 3 November 2016

Template:mpu The Xeon E5-2620 v4 is a 64-bit octa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for standard 2S environments (1U square form factor). Operating at 2.1 GHz with a turbo boost frequency of 3 GHz for a single active core, this MPU has a TDP of 85 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core, write-back)
L1D$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core, write-back)
L2$ 4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
16x256 KiB 8-way set associative (per core, write-back)
L3$ 40 MiB
40,960 KiB
41,943,040 B
0.0391 GiB
16x2.5 MiB 20-way set associative (shared, per core, write-back)
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-2620 v4 - Intel +, Xeon E5-2620 v4 - Intel + and Xeon E5-2620 v4 - Intel#io +
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
bus links2 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus speed4,000 MHz (4 GHz, 4,000,000 kHz) +
bus typeQPI +
chipsetC610 Series +
clock multiplier21 +
core count8 +
core family6 +
core model4F +
core nameBroadwell EP +
core steppingR0 +
core voltage1.82 V (18.2 dV, 182 cV, 1,820 mV) +
cpuid406F1 +
designerIntel +
die area246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) +
familyXeon E5 +
first announcedJune 20, 2016 +
first launchedJune 20, 2016 +
full page nameintel/xeon e5/e5-2620 v4 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureTrusted Execution Technology +, Transactional Synchronization Extensions +, Intel vPro Technology +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology + and Extended Page Tables +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
io voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
io voltage tolerance3% +
isax86-64 +
isa familyx86 +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ description20-way set associative +
l3$ size20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +
ldateJune 20, 2016 +
manufacturerIntel +
market segmentServer +
max case temperature347.15 K (74 °C, 165.2 °F, 624.87 °R) +
max cpu count2 +
max memory1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) +
max pcie lanes40 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureBroadwell +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberE5-2620 v4 +
nameXeon E5-2620 v4 +
part numberCM8066002032201 + and BX80660E52620V4 +
platformGrantley EP 2S +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 417.00 (€ 375.30, £ 337.77, ¥ 43,088.61) +
s-specSR2R6 +
s-spec (qs)QKES + and QKRG +
seriesE5-2000 +
smp max ways2 +
tdp85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technologyCMOS +
thread count16 +
transistor count3,200,000,000 +
turbo frequency (1 core)3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (2 cores)3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (3 cores)2,800 MHz (2.8 GHz, 2,800,000 kHz) +
turbo frequency (4 cores)2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (5 cores)2,600 MHz (2.6 GHz, 2,600,000 kHz) +
turbo frequency (6 cores)2,500 MHz (2.5 GHz, 2,500,000 kHz) +
turbo frequency (7 cores)2,400 MHz (2.4 GHz, 2,400,000 kHz) +
turbo frequency (8 cores)2,300 MHz (2.3 GHz, 2,300,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +