From WikiChip
Difference between revisions of "intel/xeon e5/e5-1650 v4"
< intel‎ | xeon e5

Line 84: Line 84:
 
}}
 
}}
 
The '''Xeon E5-1650 v4''' is a {{arch|64}} [[hexa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for 1S workstations. Operating at 3.6 GHz with a {{intel|turbo boost}} frequency of 4 GHz for a single active core, this MPU has a TDP of 140 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 
The '''Xeon E5-1650 v4''' is a {{arch|64}} [[hexa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for 1S workstations. Operating at 3.6 GHz with a {{intel|turbo boost}} frequency of 4 GHz for a single active core, this MPU has a TDP of 140 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
 +
{{cache info
 +
|l1i cache=192 KiB
 +
|l1i break=6x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1i extra=(per core, write-back)
 +
|l1d cache=192 KiB
 +
|l1d break=6x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d extra=(per core, write-back)
 +
|l2 cache=1.5 MiB
 +
|l2 break=6x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 extra=(per core, write-back)
 +
|l3 cache=15 MiB
 +
|l3 break=6x2.5 MiB
 +
|l3 desc=20-way set associative
 +
|l3 extra=(shared, per core, write-back)
 +
}}

Revision as of 12:23, 3 November 2016

Template:mpu The Xeon E5-1650 v4 is a 64-bit hexa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for 1S workstations. Operating at 3.6 GHz with a turbo boost frequency of 4 GHz for a single active core, this MPU has a TDP of 140 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 192 KiB
196,608 B
0.188 MiB
6x32 KiB 8-way set associative (per core, write-back)
L1D$ 192 KiB
196,608 B
0.188 MiB
6x32 KiB 8-way set associative (per core, write-back)
L2$ 1.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
6x256 KiB 8-way set associative (per core, write-back)
L3$ 15 MiB
15,360 KiB
15,728,640 B
0.0146 GiB
6x2.5 MiB 20-way set associative (shared, per core, write-back)
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-1650_v4&oldid=26521"
Facts about "Xeon E5-1650 v4 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description8-way set associative +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ description8-way set associative +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l3$ description20-way set associative +
l3$ size15 MiB (15,360 KiB, 15,728,640 B, 0.0146 GiB) +