From WikiChip
Difference between revisions of "intel/xeon d/d-2191"
< intel‎ | xeon d

Line 62: Line 62:
 
|l3 desc=11-way set associative
 
|l3 desc=11-way set associative
 
|l3 policy=write-back
 
|l3 policy=write-back
−
}}
 
−
 
−
== Memory controller ==
 
−
{{memory controller
 
−
|type=DDR4-2666
 
−
|ecc=Yes
 
−
|max mem=512 GiB
 
−
|controllers=2
 
−
|channels=4
 
−
|max bandwidth=79.47 GiB/s
 
−
|bandwidth schan=19.87 GiB/s
 
−
|bandwidth dchan=39.74 GiB/s
 
−
|bandwidth qchan=79.47 GiB/s
 
−
}}
 
−
 
−
== Expansions ==
 
−
{{expansions main
 
−
|
 
−
{{expansions entry
 
−
|type=PCIe
 
−
|pcie revision=3.0
 
−
|pcie lanes=48
 
−
|pcie config=x16
 
−
|pcie config 2=x8
 
−
|pcie config 3=x4
 
−
}}
 
−
}}
 
−
 
−
== Features ==
 
−
{{x86 features
 
−
|real=Yes
 
−
|protected=Yes
 
−
|smm=Yes
 
−
|fpu=Yes
 
−
|x8616=Yes
 
−
|x8632=Yes
 
−
|x8664=Yes
 
−
|nx=Yes
 
−
|mmx=Yes
 
−
|emmx=Yes
 
−
|sse=Yes
 
−
|sse2=Yes
 
−
|sse3=Yes
 
−
|ssse3=Yes
 
−
|sse41=Yes
 
−
|sse42=Yes
 
−
|sse4a=No
 
−
|avx=Yes
 
−
|avx2=Yes
 
−
|avx512f=Yes
 
−
|avx512cd=Yes
 
−
|avx512er=No
 
−
|avx512pf=No
 
−
|avx512bw=Yes
 
−
|avx512dq=Yes
 
−
|avx512vl=Yes
 
−
|avx512ifma=No
 
−
|avx512vbmi=No
 
−
|avx5124fmaps=No
 
−
|avx5124vnniw=No
 
−
|avx512vpopcntdq=No
 
−
|avx512units=2
 
−
|abm=Yes
 
−
|tbm=No
 
−
|bmi1=Yes
 
−
|bmi2=Yes
 
−
|fma3=Yes
 
−
|fma4=No
 
−
|aes=Yes
 
−
|rdrand=Yes
 
−
|sha=No
 
−
|xop=No
 
−
|adx=Yes
 
−
|clmul=Yes
 
−
|f16c=Yes
 
−
|tbt1=No
 
−
|tbt2=Yes
 
−
|tbmt3=No
 
−
|bpt=No
 
−
|eist=Yes
 
−
|sst=Yes
 
−
|flex=No
 
−
|fastmem=No
 
−
|ivmd=Yes
 
−
|intelnodecontroller=No
 
−
|intelnode=No
 
−
|kpt=No
 
−
|ptt=No
 
−
|intelrunsure=No
 
−
|mbe=No
 
−
|isrt=No
 
−
|sba=No
 
−
|mwt=No
 
−
|sipp=No
 
−
|att=No
 
−
|ipt=Yes
 
−
|tsx=Yes
 
−
|txt=Yes
 
−
|ht=Yes
 
−
|vpro=Yes
 
−
|vtx=Yes
 
−
|vtd=Yes
 
−
|ept=Yes
 
−
|mpx=Yes
 
−
|sgx=No
 
−
|securekey=Yes
 
−
|osguard=Yes
 
−
|intqat=No
 
−
|3dnow=No
 
−
|e3dnow=No
 
−
|smartmp=No
 
−
|powernow=No
 
−
|amdvi=No
 
−
|amdv=No
 
−
|amdsme=No
 
−
|amdtsme=No
 
−
|amdsev=No
 
−
|rvi=No
 
−
|smt=No
 
−
|sensemi=No
 
−
|xfr=No
 
 
}}
 
}}

Revision as of 15:55, 7 February 2018

Edit Values
Xeon D-2191
skylake-de (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberD-2191
MarketServer, Embedded
IntroductionFebruary 7, 2018 (announced)
February 7, 2018 (launched)
Release Price$2406
ShopAmazon
General Specs
FamilyXeon D
SeriesD-2000
LockedYes
Frequency1,600 MHz
Turbo Frequency3,000 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier16
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
Core NameSkylake-DE
Core SteppingM1
Process14 nm
TechnologyCMOS
MCPYes (2 dies)
Word Size64 bit
Cores18
Threads36
Max Memory512 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP86 W
Packaging
PackageFCBGA-2518 (BGA)
Dimension45 mm x 52.5 mm
Contacts2518

Xeon D-2191 is a 64-bit 18-core high-performance x86 server microprocessor introduced by Intel in early 2018 for the dense server and edge computing market segment. Fabricated on Intel's 14 nm process based on the Skylake microarchitecture, this model operates at 1.6 GHz with a Turbo Boost of up to 3.0 GHz and a TDP of 86 W. The D-2191 supports up to 512 GiB of quad-chanel DDR4-2400 ECC memory.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.125 MiB
1,152 KiB
1,179,648 B
L1I$576 KiB
589,824 B
0.563 MiB
18x32 KiB8-way set associative 
L1D$576 KiB
589,824 B
0.563 MiB
18x32 KiB8-way set associativewrite-back
L2$18 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
  18x1 MiB16-way set associativewrite-back
L3$24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
  18x1.375 MiB11-way set associativewrite-back
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_d/d-2191&oldid=73842"
Facts about "Xeon D-2191 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon D-2191 - Intel#package +
base frequency1,600 MHz (1.6 GHz, 1,600,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
clock multiplier16 +
core count18 +
core nameSkylake-DE +
core steppingM1 +
designerIntel +
die count2 +
familyXeon D +
first announcedFebruary 7, 2018 +
first launchedFebruary 7, 2018 +
full page nameintel/xeon d/d-2191 +
has locked clock multipliertrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size1,152 KiB (1,179,648 B, 1.125 MiB) +
l1d$ description8-way set associative +
l1d$ size576 KiB (589,824 B, 0.563 MiB) +
l1i$ description8-way set associative +
l1i$ size576 KiB (589,824 B, 0.563 MiB) +
l2$ description16-way set associative +
l2$ size18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) +
l3$ description11-way set associative +
l3$ size24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) +
ldateFebruary 7, 2018 +
main imageFile:skylake-de (front).png +
manufacturerIntel +
market segmentServer + and Embedded +
max cpu count1 +
max memory524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
microarchitectureSkylake (server) +
model numberD-2191 +
nameXeon D-2191 +
packageFCBGA-2518 +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 2,406.00 (€ 2,165.40, £ 1,948.86, ¥ 248,611.98) +
seriesD-2000 +
smp max ways1 +
tdp86 W (86,000 mW, 0.115 hp, 0.086 kW) +
technologyCMOS +
thread count36 +
turbo frequency (1 core)3,000 MHz (3 GHz, 3,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +