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{{intel title|Tremont|arch}}
 +
{{microarchitecture
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|atype=CPU
 +
|name=Tremont
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|designer=Intel
 +
|manufacturer=Intel
 +
|introduction=2019
 +
|process=10 nm
 +
|type=Superscalar
 +
|oooe=Yes
 +
|speculative=Yes
 +
|renaming=Yes
 +
|isa=x86-64
 +
|extension=MOVBE
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|extension 2=MMX
 +
|extension 3=SSE
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|extension 4=SSE2
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|extension 5=SSE3
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|extension 6=SSSE3
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|extension 7=SSE4.1
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|extension 8=SSE4.2
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|extension 9=POPCNT
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|extension 10=AES
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|extension 11=PCLMUL
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|extension 12=RDRND
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|extension 13=XSAVE
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|extension 14=XSAVEOPT
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|extension 15=FSGSBASE
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|extension 16=PTWRITE
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|extension 17=RDPID
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|extension 18=SGX
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|extension 19=UMIP
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|extension 20=GFNI-SSE
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|extension 21=CLWB
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|extension 22=ENCLV
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|extension 23=SHA
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|core name=Elkhart Lake
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|core name 2=Jasper Lake
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|core name 3=Skyhawk Lake
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|predecessor=Goldmont Plus
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|predecessor link=intel/microarchitectures/goldmont plus
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|successor=Gracemont
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|successor link=intel/microarchitectures/gracemont
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}}
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'''Tremont''' is [[Intel]]'s successor to {{\\|Goldmont Plus}}, a [[10 nm]] microarchitecture for ultra-low power devices and microservers.
  
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== Codenames ==
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{| class="wikitable"
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! Platform !! Core Name || PCH
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|-
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| || {{intel|Skyhawk Lake|l=core}} ||
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|-
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| Jacobsville || {{intel|Elkhart Lake|l=core}} || {{intel|Mule Creek Canyon|l=chipset}}
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|-
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| || {{intel|Jasper Lake|l=core}} ||
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|}
 +
 +
== Brands ==
 +
{{empty section}}
 +
 +
== Release Dates ==
 +
Tremont was released in a number of products in late 2019.
 +
 +
== Technology ==
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Tremont uses Intel's [[10 nm process]].
 +
 +
== Compiler support ==
 +
{| class="wikitable"
 +
|-
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! Compiler !! Arch-Specific || Arch-Favorable
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|-
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| [[ICC]] || <code>-march=tremont</code> || <code>-mtune=tremont</code>
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|-
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| [[GCC]] || <code>-march=tremont</code> || <code>-mtune=tremont</code>
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|-
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| [[LLVM]] || <code>-march=tremont</code> || <code>-mtune=tremont</code>
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|-
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| [[Visual Studio]] || <code>/arch:?</code> || <code>/tune:?</code>
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|}
 +
 +
=== CPUID ===
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{| class="wikitable tc1 tc2 tc3 tc4"
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! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
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|-
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| rowspan="2" | ? || 0 || 0x6 || 0x8 || 0x6
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|-
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| colspan="4" | Family 6 Model 134
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|}
 +
 +
== Architecture ==
 +
Tremont is designed with significant single-thread performance in mind while focusing on low-power small silicon area cores.
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=== Key changes from {{\\|Goldmont Plus}} ===
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* Significant [[IPC]] uplift ([[Intel]] self-reported average 32% IPC accross proxy benchmarks such as [[SPEC CPU2006]]/[[SPEC CPU2017]])
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* Front-end
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** Redesigned front-end
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*** New dual symmetric decode cluster
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**** Out-of-order decode
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**** 6-wide decode
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***** 3-way decode per cluster
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** Smarter [[prefetchers]]
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** Improved [[branch predictor]]
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*** Big-core level of performance
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* Back-end
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** larger ROB
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** wide issue (10-wide)
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* Execution Engine
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** 2x store data ports (up from 1)
 +
 +
 +
====New instructions ====
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Tremont introduced a number of {{x86|extensions|new instructions}}:
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 +
* {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush
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* {{x86|ENCLV|<code>ENCLV</code>}} - SGX oversubscription instructions
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* {{x86|CLDEMOTE|<code>CLDEMOTE</code>}} - Cache line demote instruction
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* {{x86|SSE_GFNI|<code>SSE_GFNI</code>}} - SSE-based Galois Field New Instructions
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* Direct store instructions: MOVDIRI, MOVDIR64B
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* User wait instructions: TPAUSE, UMONITOR, UMWAIT
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* Split Lock Detection - detection and cause an exception for split locks
 +
 +
=== Block Diagram ===
 +
==== Individual Core ====
 +
:[[File:tremont block diagram.svg|850px]]

Latest revision as of 23:05, 23 March 2020

Edit Values
Tremont µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2019
Process10 nm
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB, ENCLV, SHA
Cores
Core NamesElkhart Lake,
Jasper Lake,
Skyhawk Lake
Succession

Tremont is Intel's successor to Goldmont Plus, a 10 nm microarchitecture for ultra-low power devices and microservers.

Codenames[edit]

Platform Core Name PCH
Skyhawk Lake
Jacobsville Elkhart Lake Mule Creek Canyon
Jasper Lake

Brands[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Release Dates[edit]

Tremont was released in a number of products in late 2019.

Technology[edit]

Tremont uses Intel's 10 nm process.

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
ICC -march=tremont -mtune=tremont
GCC -march=tremont -mtune=tremont
LLVM -march=tremont -mtune=tremont
Visual Studio /arch:? /tune:?

CPUID[edit]

Core Extended
Family
Family Extended
Model
Model
 ? 0 0x6 0x8 0x6
Family 6 Model 134

Architecture[edit]

Tremont is designed with significant single-thread performance in mind while focusing on low-power small silicon area cores.

Key changes from Goldmont Plus[edit]

  • Significant IPC uplift (Intel self-reported average 32% IPC accross proxy benchmarks such as SPEC CPU2006/SPEC CPU2017)
  • Front-end
    • Redesigned front-end
      • New dual symmetric decode cluster
        • Out-of-order decode
        • 6-wide decode
          • 3-way decode per cluster
    • Smarter prefetchers
    • Improved branch predictor
      • Big-core level of performance
  • Back-end
    • larger ROB
    • wide issue (10-wide)
  • Execution Engine
    • 2x store data ports (up from 1)


New instructions[edit]

Tremont introduced a number of new instructions:

  • CLWB - Force cache line write-back without flush
  • ENCLV - SGX oversubscription instructions
  • CLDEMOTE - Cache line demote instruction
  • SSE_GFNI - SSE-based Galois Field New Instructions
  • Direct store instructions: MOVDIRI, MOVDIR64B
  • User wait instructions: TPAUSE, UMONITOR, UMWAIT
  • Split Lock Detection - detection and cause an exception for split locks

Block Diagram[edit]

Individual Core[edit]

tremont block diagram.svg
codenameTremont +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/tremont +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameTremont +
process10 nm (0.01 μm, 1.0e-5 mm) +