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== History == | == History == | ||
[[File:intel 2019 investor meeting tiger lake roadmap.png|right|thumb|Intel 2019 and 2020 Roadmap]] | [[File:intel 2019 investor meeting tiger lake roadmap.png|right|thumb|Intel 2019 and 2020 Roadmap]] | ||
− | Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in | + | Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in 2021. |
== Architecture == | == Architecture == |
Facts about "Tiger Lake - Microarchitectures - Intel"
codename | Tiger Lake + |
core count | 2 +, 4 +, 6 + and 8 + |
designer | Intel + |
first launched | September 2, 2020 + |
full page name | intel/microarchitectures/tiger lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Tiger Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |