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Prior to Skylake, SpeedStep had three major domains: [[Cores]], [[Integrated Graphics]], and Coherent Fabric. With Skylake, SpeedStep has been extended to a number of new domains, including the [[System Agent]], Memory, and the [[eDRAM]] I/O. Depending on the bandwidth consumption, SpeedStep can now save energy by reducing frequency on the new domains. | Prior to Skylake, SpeedStep had three major domains: [[Cores]], [[Integrated Graphics]], and Coherent Fabric. With Skylake, SpeedStep has been extended to a number of new domains, including the [[System Agent]], Memory, and the [[eDRAM]] I/O. Depending on the bandwidth consumption, SpeedStep can now save energy by reducing frequency on the new domains. | ||
− | Information from the new domains, including additional thermal | + | Information from the new domains, including additional thermal ski temperature control information is now supplied to OEMs. |
==== Power of System (Psys) ==== | ==== Power of System (Psys) ==== |
Facts about "Skylake (client) - Microarchitectures - Intel"
codename | Skylake (client) + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | August 5, 2015 + |
full page name | intel/microarchitectures/skylake (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Skylake (client) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |