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Latest revision | Your text | ||
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− | {{intel title|Skylake | + | {{intel title|Skylake|arch}} |
{{microarchitecture | {{microarchitecture | ||
|atype=CPU | |atype=CPU | ||
− | |name=Skylake | + | |name=Skylake |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
Line 9: | Line 9: | ||
|cores=2 | |cores=2 | ||
|cores 2=4 | |cores 2=4 | ||
+ | |cores 3=6 | ||
+ | |cores 4=8 | ||
+ | |cores 5=10 | ||
+ | |cores 6=12 | ||
+ | |cores 7=14 | ||
+ | |cores 8=16 | ||
+ | |cores 9=18 | ||
+ | |cores 10=20 | ||
+ | |cores 11=22 | ||
+ | |cores 12=24 | ||
+ | |cores 13=26 | ||
+ | |cores 14=28 | ||
|type=Superscalar | |type=Superscalar | ||
− | |||
|oooe=Yes | |oooe=Yes | ||
|speculative=Yes | |speculative=Yes | ||
Line 16: | Line 27: | ||
|stages min=14 | |stages min=14 | ||
|stages max=19 | |stages max=19 | ||
− | |isa=x86-64 | + | |isa=x86-16 |
+ | |isa 2=x86-32 | ||
+ | |isa 3=x86-64 | ||
+ | |extension=MOVBE | ||
|extension 2=MMX | |extension 2=MMX | ||
|extension 3=SSE | |extension 3=SSE | ||
Line 39: | Line 53: | ||
|extension 22=TXT | |extension 22=TXT | ||
|extension 23=TSX | |extension 23=TSX | ||
+ | |extension 24=RDSEED | ||
|extension 25=ADCX | |extension 25=ADCX | ||
+ | |extension 26=PREFETCHW | ||
|extension 27=CLFLUSHOPT | |extension 27=CLFLUSHOPT | ||
|extension 28=XSAVE | |extension 28=XSAVE | ||
+ | |extension 29=SGX | ||
+ | |extension 30=MPX | ||
+ | |extension 31=AVX-512 | ||
|l1i=32 KiB | |l1i=32 KiB | ||
|l1i per=core | |l1i per=core | ||
Line 62: | Line 81: | ||
|core name 4=Skylake S | |core name 4=Skylake S | ||
|core name 5=Skylake DT | |core name 5=Skylake DT | ||
+ | |core name 6=Skylake X | ||
+ | |core name 7=Skylake SP | ||
|predecessor=Broadwell | |predecessor=Broadwell | ||
|predecessor link=intel/microarchitectures/broadwell | |predecessor link=intel/microarchitectures/broadwell | ||
|successor=Kaby Lake | |successor=Kaby Lake | ||
|successor link=intel/microarchitectures/kaby lake | |successor link=intel/microarchitectures/kaby lake | ||
− | |||
− | |||
|pipeline=Yes | |pipeline=Yes | ||
|OoOE=Yes | |OoOE=Yes | ||
Line 73: | Line 92: | ||
|core names=Yes | |core names=Yes | ||
}} | }} | ||
− | '''Skylake''' ('''SKL''') | + | '''Skylake''' ('''SKL''') is [[Intel]]'s successor to {{\\|Broadwell}}, a [[14 nm process]] [[microarchitecture]] for mainstream desktops, servers, and mobile devices. Skylake succeeded the short-lived {{\\|Broadwell}} which experienced severe delays. Skylake is the "Architecture" phase as part of Intel's {{intel|PAO}} model. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]]. |
− | For desktop and mobile, Skylake is branded as 6th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}, {{intel|Core i7}} processors. For workstations it's branded as {{intel|Xeon E3|Xeon E3 v5}}. | + | For desktop and mobile, Skylake is branded as 6th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}, {{intel|Core i7}}, and {{intel|Core i9}} processors. For workstations it's branded as {{intel|Xeon E3|Xeon E3 v5}} For scalable server class processors, Intel branded it as {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}}. |
== Codenames == | == Codenames == | ||
− | |||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! Core !! Abbrev | + | ! Core !! Abbrev !! Target |
|- | |- | ||
− | | {{intel|Skylake Y|l=core}} || SKL-Y | + | | {{intel|Skylake Y|l=core}} || SKL-Y || 2-in-1s detachable, tablets, and computer sticks |
|- | |- | ||
− | | {{intel|Skylake U|l=core}} || SKL-U | + | | {{intel|Skylake U|l=core}} || SKL-U || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
|- | |- | ||
− | | {{intel|Skylake H|l=core}} || SKL-H | + | | {{intel|Skylake H|l=core}} || SKL-H || Ultimate mobile performance, mobile workstations |
|- | |- | ||
− | | {{intel|Skylake S|l=core}} || SKL-S | + | | {{intel|Skylake S|l=core}} || SKL-S || Desktop performance to value, AiOs, and minis |
|- | |- | ||
− | | {{intel|Skylake | + | | {{intel|Skylake X|l=core}} || SKL-X || High-end desktops & enthusiasts market |
+ | |- | ||
+ | | {{intel|Skylake DT|l=core}} || SKL-DT || Workstations & entry-level servers | ||
+ | |- | ||
+ | | colspan="3" | | ||
+ | |- | ||
+ | | {{intel|Skylake SP|l=core}} || SKL-SP || Server Scalable Processors | ||
|} | |} | ||
== Brands == | == Brands == | ||
− | + | [[File:xeon scalable family decode.png|thumb|right|250px|New Xeon branding]] | |
− | Intel released Skylake under | + | Intel released Skylake under 7 main brand families. |
+ | |||
+ | Additionally, Intel introduced a number of new server chip families with the introduction of {{intel|Skylake SP|l=core}}. | ||
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | ||
Line 102: | Line 128: | ||
! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="7" | Differentiating Features | ! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="7" | Differentiating Features | ||
|- | |- | ||
− | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] | + | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{x86|AVX-512}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]] |
+ | |- | ||
+ | | rowspan="2" | [[File:intel celeron (2015).png|50px|link=intel/celeron]] || rowspan="2" | {{intel|Celeron}} || style="text-align: left;" | Entry-level Budget || rowspan="2" | [[dual-core|dual]] || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} | ||
+ | |- | ||
+ | | style="text-align: left;" | Entry-level Budget (Embedded) || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}} | ||
+ | |- | ||
+ | | rowspan="2" | [[File:intel pentium (2015).png|50px|link=intel/pentium_(2009)]] || rowspan="2" | {{intel|Pentium (2009)|Pentium}} || style="text-align: left;" | Budget (Mobile) || rowspan="2" | dual || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} | ||
|- | |- | ||
− | + | | style="text-align: left;" | Budget (Desktop) || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}} | |
|- | |- | ||
− | | style="text-align: left;" | | + | | rowspan="2" | [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || rowspan="2" | {{intel|Core i3}} || style="text-align: left;" | Low-end Performance || rowspan="2" | dual || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} |
|- | |- | ||
− | + | | style="text-align: left;" | Low-end Performance<br>(Desktop/Embedded) || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}} | |
|- | |- | ||
− | | style="text-align: left;" | | + | | rowspan="2" | [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || rowspan="2" | {{intel|Core i5}} || rowspan="2" style="text-align: left;" | Mid-range Performance || dual || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}} || {{tchk|no}} |
|- | |- | ||
− | + | |[[quad-core|quad]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}} || {{tchk|no}} | |
|- | |- | ||
− | | style="text-align: left;" | | + | | rowspan="3" | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || rowspan="3" | {{intel|Core i7}} || rowspan="2" style="text-align: left;" | High-end Performance || dual || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}} || {{tchk|no}} |
|- | |- | ||
− | | | + | |quad || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}} || {{tchk|no}} |
|- | |- | ||
− | |[[ | + | |style="text-align: left;" | Enthusiasts/High Performance ({{intel|Skylake X|X|l=core}}) || [[6 cores|6]] - [[8 cores|8]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} |
|- | |- | ||
− | + | | [[File:xeon logo (2015).png|50px|link=intel/xeon e3]] || {{intel|Xeon E3}} || style="text-align: left;" | Workstation/dense servers || quad || {{tchk|some}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}} || {{tchk|yes}} | |
|- | |- | ||
− | | | + | | [[File:core i9x logo.png|50px|link=intel/core_i9]] || {{intel|Core i9}} || style="text-align: left;" | Enthusiasts/High Performance || [[10 cores|10]] - [[18 cores|18]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} |
|- | |- | ||
− | | [[File:xeon | + | ! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="7" | Differentiating Features |
+ | |- | ||
+ | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{intel|Turbo Boost|TBT}} !! {{x86|AVX-512}} !! AVX-512 Units !! {{intel|Ultra Path Interconnect|UPI}} links !! Scalability | ||
+ | |- | ||
+ | | [[File:xeon bronze (2017).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || [[6 cores|6]] - [[8 cores|8]] || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}} || 1 || 2 || Up to 2 | ||
+ | |- | ||
+ | | [[File:xeon silver (2017).png|50px]] || {{intel|Xeon Silver}} || style="text-align: left;" | Mid-range performance / <br>Efficient lower power || [[4 cores|4]] - [[12 cores|12]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 1 || 2 || Up to 2 | ||
+ | |- | ||
+ | | rowspan="2" | [[File:xeon gold (2017).png|50px]] || {{intel|Xeon Gold}} 5000 || style="text-align: left;" | High performance || [[4 cores|4]] - [[14 cores|14]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 1 || 2 || Up to 4 | ||
+ | |- | ||
+ | | {{intel|Xeon Gold}} 6000 || style="text-align: left;" | Higher performance || [[6 cores|6]] - [[22 cores|22]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 2 || 3 || Up to 4 | ||
+ | |- | ||
+ | | [[File:xeon platinum (2017).png|50px]] || {{intel|Xeon Platinum}} || style="text-align: left;" | Highest performance / flexibility || [[4 cores|4]] - [[28 cores|28]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 2 || 3 || Up to 8 | ||
|} | |} | ||
== Release Dates == | == Release Dates == | ||
− | Skylake was first demonstrated at the 2014 Intel Developer Forum in San Francisco on September 9 with the goals of launching in the second half of 2015. | + | Skylake was first demonstrated at the 2014 Intel Developer Forum in San Francisco on September 9 with the goals of launching in the second half of 2015. Skylake-based {{intel|Core X}} was introduced in May 2017 while {{intel|Skylake SP|l=core}} was introduced in July 2017. |
== Process Technology == | == Process Technology == | ||
{{main|intel/microarchitectures/broadwell#Process_Technology|l1=Broadwell § Process Technology}} | {{main|intel/microarchitectures/broadwell#Process_Technology|l1=Broadwell § Process Technology}} | ||
− | Skylake uses the same [[14 nm process]] used for the Broadwell microarchitecture for all mainstream consumer parts (Core, Celeron, et al). | + | Skylake uses the same [[14 nm process]] used for the Broadwell microarchitecture for all mainstream consumer parts (Core, Celeron, et al). Unlike mainstream Skylake models, the enthusiasts ({{intel|Skylake X|l=core}}) models are fabricated on Intel's enhanced 14+ nm process which is used by {{\\|Kaby Lake}} (see {{intel|kaby lake#Process_Technology|Kaby Lake § Process Technology}} for more info). |
== Compatibility == | == Compatibility == | ||
Line 138: | Line 182: | ||
! Vendor !! OS !! Version !! Notes | ! Vendor !! OS !! Version !! Notes | ||
|- | |- | ||
− | | rowspan="4" | | + | | rowspan="4" | Microsoft || rowspan="4" | Windows || style="background-color: #ffdad6;" | Windows Vista || No Support |
|- | |- | ||
− | | style="background-color: #d6ffd8;" | Windows 7 || rowspan="2" | Support ends July | + | | style="background-color: #d6ffd8;" | Windows 7 || rowspan="2" | Support ends July 2017 |
|- | |- | ||
| style="background-color: #d6ffd8;" | Windows 8.1 | | style="background-color: #d6ffd8;" | Windows 8.1 | ||
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| colspan="4" | Family 6 Model 78 | | colspan="4" | Family 6 Model 78 | ||
|- | |- | ||
− | | rowspan="2" | {{intel|Skylake DT|DT|l=core}}/{{intel|Skylake H|H|l=core}}/{{intel|Skylake S|S|l=core}} || 0 || 0x6 || 0x5 || 0xE | + | | rowspan="2" | {{intel|Skylake DT|DT|l=core}}/{{intel|Skylake H|H|l=core}}/{{intel|Skylake S|S|l=core}}/{{intel|Skylake X|X|l=core}} || 0 || 0x6 || 0x5 || 0xE |
|- | |- | ||
| colspan="4" | Family 6 Model 94 | | colspan="4" | Family 6 Model 94 | ||
+ | |- | ||
+ | | rowspan="2" | {{intel|Skylake SP|SP|l=core}} || 0 || 0x6 || 0x5 || 0x5 | ||
+ | |- | ||
+ | | colspan="4" | Family 6 Model 85 | ||
|} | |} | ||
Line 193: | Line 241: | ||
**** {{intel|Skylake Y|l=core}} and Skylake U cores have chipset in the same package (simplified {{intel|on Package I/O|OPIO}}) | **** {{intel|Skylake Y|l=core}} and Skylake U cores have chipset in the same package (simplified {{intel|on Package I/O|OPIO}}) | ||
**** Increase in transfer rate from 5.0 GT/s to 8.0 GT/s (~3.93GB/s up from 2GB/s) per lane | **** Increase in transfer rate from 5.0 GT/s to 8.0 GT/s (~3.93GB/s up from 2GB/s) per lane | ||
− | **** Limits motherboard trace design to 7 inches max from | + | **** Limits motherboard trace design to 7 inches max from (down from 8) from the CPU to chipset |
** PCIe & DMI upgraded to Gen3 | ** PCIe & DMI upgraded to Gen3 | ||
** More I/O (configurable as PCIe/SATA/USB3) | ** More I/O (configurable as PCIe/SATA/USB3) | ||
Line 199: | Line 247: | ||
** CSI-2 for the integrated IPU (mobile SKUs) | ** CSI-2 for the integrated IPU (mobile SKUs) | ||
** Intel Sensor Solution Hub integration | ** Intel Sensor Solution Hub integration | ||
− | |||
− | |||
* [[System Agent]] | * [[System Agent]] | ||
** New Image Processing Unit (IPU) | ** New Image Processing Unit (IPU) | ||
Line 208: | Line 254: | ||
* Core | * Core | ||
** Front End | ** Front End | ||
+ | *** Larger legacy pipeline delivery (5 µOPs, up from 4) | ||
+ | **** Another simple decoder has been added. | ||
*** Allocation Queue (IDQ) | *** Allocation Queue (IDQ) | ||
− | |||
**** Larger delivery (6 µOPs, up from 4) | **** Larger delivery (6 µOPs, up from 4) | ||
**** 2.28x larger buffer (64/thread, up from 56) | **** 2.28x larger buffer (64/thread, up from 56) | ||
Line 229: | Line 276: | ||
*** Page split load penalty reduced 20-fold | *** Page split load penalty reduced 20-fold | ||
*** Larger Write-back buffer | *** Larger Write-back buffer | ||
+ | *** Larger Line Fill Buffer? | ||
* Memory | * Memory | ||
Line 255: | Line 303: | ||
** Direct X 12, OpenCL 2.0, OpenGL 4.4 | ** Direct X 12, OpenCL 2.0, OpenGL 4.4 | ||
** Up to 24 EUs GT2 (same as {{\\|Haswell}}); 48 EUs for GT3, and up to 72 EUs on {{intel|Iris Pro Graphics}} | ** Up to 24 EUs GT2 (same as {{\\|Haswell}}); 48 EUs for GT3, and up to 72 EUs on {{intel|Iris Pro Graphics}} | ||
− | *** | + | *** 1,152 GFLOPS @ 1 GHz |
+ | |||
+ | ==== Server ==== | ||
+ | [[File:skylake sp buffer windows.png|right|350px]] | ||
+ | Unlike client models, Skylake servers and HEDT models will still incorporate the fully integrated voltage regulator (FIVR) on-die. Those chips also have an entirely new multi-core architecture along with a new [[mesh topology]] interconnect network (from [[ring topology]]). | ||
+ | |||
+ | * Improved "14 nm+" process (see {{\\|kaby_lake#Process_Technology|Kaby Lake § Process Technology}}) | ||
+ | * {{intel|Omni-Path Architecture}} (OPA) | ||
+ | * Mesh architecture | ||
+ | ** {{intel|Sub-NUMA Clustering}} (SNC) support (replaces the {{intel|Cluster-on-Die}} (COD) implementation) | ||
+ | * Core | ||
+ | ** Front-end | ||
+ | *** LSD is disabled | ||
+ | ** Back-end | ||
+ | *** Port 4 now performs 512b stores (from 256b) | ||
+ | *** Port 0 & Port 1 can now be fused to perform AVX-512 | ||
+ | *** Port 5 now can do full 512b operations (not on all models) | ||
+ | ** Memory Subsystem | ||
+ | *** Store is now 64B/cycle (from 32B/cycle) | ||
+ | *** Load is now 2x64B/cycle (from 2x32B/cycle) | ||
+ | * Memory | ||
+ | ** L2$ | ||
+ | *** Increased to 1 MiB/core (from 250 KiB/core) | ||
+ | ** L3$ | ||
+ | *** Was made non-inclusive (from inclusive) | ||
+ | *** Reduced to 1.375 MiB/core (from 2.5 MiB/core) | ||
+ | ** DRAM | ||
+ | *** hex-channel DDR4-2666 (from quad-channel) | ||
==== CPU changes ==== | ==== CPU changes ==== | ||
− | * | + | * Most ALU operations have 4 op/cycle 1 for 8 and 32-bit registers. 64-bit ops are still limited to 3 op/cycle. (16-bit throughput varies per op, can be 4, 3.5 or 2 op/cycle). |
− | * | + | * MOVSX and MOVZX have 4 op/cycle throughput for 16->32 and 32->64 forms, in addition to Haswell's 8->32, 8->64 and 16->64 bit forms. |
− | * Vector moves have throughput of 4 op/cycle ( | + | * ADC and SBB have throughput of 1 op/cycle, same as Haswell. |
− | * | + | * Vector moves have throughput of 4 op/cycle (move elimination). |
− | * Vector ALU ops are often "standardized" to latency of 4. for example, vADDPS and vMULPS used to have L of 3 and 5 | + | * Not only zeroing vector vpXORxx and vpSUBxx ops, but also vPCMPxxx on the same register, have throughput of 4 op/cycle. |
− | * Fused multiply-add ops have latency of 4 and throughput of 0.5 op/cycle | + | * Vector ALU ops are often "standardized" to latency of 4. for example, vADDPS and vMULPS used to have L of 3 and 5, now both are 4. |
− | * Throughput of vADDps, vSUBps, vCMPps, vMAXps, their scalar and double analogs is increased to 2 op/cycle | + | * Fused multiply-add ops have latency of 4 and throughput of 0.5 op/cycle. |
− | * Throughput of vPSLxx and vPSRxx with immediate (i.e. fixed vector shifts) is increased to 2 op/cycle | + | * Throughput of vADDps, vSUBps, vCMPps, vMAXps, their scalar and double analogs is increased to 2 op/cycle. |
+ | * Throughput of vPSLxx and vPSRxx with immediate (i.e. fixed vector shifts) is increased to 2 op/cycle. | ||
* Throughput of vANDps, vANDNps, vORps, vXORps, their scalar and double analogs, vPADDx, vPSUBx is increased to 3 op/cycle. | * Throughput of vANDps, vANDNps, vORps, vXORps, their scalar and double analogs, vPADDx, vPSUBx is increased to 3 op/cycle. | ||
* vDIVPD, vSQRTPD have approximately twice as good throughput: from 8 to 4 and from 28 to 12 cycles/op. | * vDIVPD, vSQRTPD have approximately twice as good throughput: from 8 to 4 and from 28 to 12 cycles/op. | ||
Line 271: | Line 347: | ||
====New instructions ==== | ====New instructions ==== | ||
− | |||
Skylake introduced a number of {{x86|extensions|new instructions}}: | Skylake introduced a number of {{x86|extensions|new instructions}}: | ||
− | * {{x86|SGX1|<code>SGX1</code>}} - Software Guard Extensions, Version 1 | + | * Client: |
− | * {{x86|MPX|<code>MPX</code>}} -Memory Protection Extensions | + | ** {{x86|SGX1|<code>SGX1</code>}} - Software Guard Extensions, Version 1 |
− | * {{x86|XSAVEC|<code>XSAVEC</code>}} - Save processor extended states with compaction to memory | + | ** {{x86|MPX|<code>MPX</code>}} -Memory Protection Extensions |
− | * {{x86|XSAVES|<code>XSAVES</code>}} - Save processor supervisor-mode extended states to memory. | + | ** {{x86|XSAVEC|<code>XSAVEC</code>}} - Save processor extended states with compaction to memory |
− | * {{x86|CLFLUSHOPT|<code>CLFLUSHOPT</code>}} - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..) | + | ** {{x86|XSAVES|<code>XSAVES</code>}} - Save processor supervisor-mode extended states to memory. |
+ | ** {{x86|CLFLUSHOPT|<code>CLFLUSHOPT</code>}} - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..) | ||
+ | * Server | ||
+ | ** ''(everything from Client)'' | ||
+ | ** {{x86|AVX-512|<code>AVX-512</code>}}, specifically: | ||
+ | *** {{x86|AVX512F|<code>AVX512F</code>}} - AVX-512 Foundation | ||
+ | *** {{x86|AVX512CD|<code>AVX512CD</code>}} - AVX-512 Conflict Detection | ||
+ | *** {{x86|AVX512BW|<code>AVX512BW</code>}} - AVX-512 Byte and Word | ||
+ | *** {{x86|AVX512BW|<code>AVX512DQ</code>}} - AVX-512 Doubleword and Quadword | ||
+ | *** {{x86|AVX512BW|<code>AVX512VL</code>}} - AVX-512 Vector Length | ||
+ | ** {{x86|PKU|<code>PKU</code>}} - Memory Protection Keys for Userspace | ||
+ | ** {{x86|PCOMMIT|<code>PCOMMIT</code>}} - PCOMMIT instruction | ||
+ | ** {{x86|CLWB|<code>CLWB</code>}} - CLWB instruction | ||
=== Block Diagram === | === Block Diagram === | ||
+ | ==== Client SoC ==== | ||
− | ==== Entire SoC Overview (dual) ==== | + | ====== Entire SoC Overview (dual) ====== |
[[File:skylake soc block diagram (dual).svg|800px]] | [[File:skylake soc block diagram (dual).svg|800px]] | ||
− | ==== Entire SoC Overview (quad) ==== | + | ====== Entire SoC Overview (quad) ====== |
[[File:skylake soc block diagram.svg|900px]] | [[File:skylake soc block diagram.svg|900px]] | ||
− | ==== Individual Core ==== | + | ====== Individual Core ====== |
− | [[File:skylake block diagram.svg | + | [[File:skylake block diagram.svg]] |
− | ==== Gen9 ==== | + | ====== Gen9 ====== |
See {{intel|Gen9#Gen9|l=arch}}. | See {{intel|Gen9#Gen9|l=arch}}. | ||
+ | |||
+ | ==== Server MPUs ==== | ||
+ | ===== Server Chip ===== | ||
+ | Note that the LCC die is identical without the two bottom rows. The XCC (28-core) die has one additional row and two additional columns of cores. Otherwise the die is identical. | ||
+ | [[File:skylake sp hcc block diagram.svg|650px]] | ||
+ | |||
+ | * '''CHA''' - Caching and Home Agent | ||
+ | * '''SF''' - Snooping Filter | ||
+ | |||
+ | ===== Individual Core ===== | ||
+ | [[File:skylake server block diagram.svg|1100px]] | ||
=== Memory Hierarchy === | === Memory Hierarchy === | ||
+ | ==== Client ==== | ||
Other than a few organizational changes (e.g. L2$ went from 8-way to 4-way set associative), the overall memory structure is identical to {{\\|Broadwell}}/{{\\|Haswell}}. | Other than a few organizational changes (e.g. L2$ went from 8-way to 4-way set associative), the overall memory structure is identical to {{\\|Broadwell}}/{{\\|Haswell}}. | ||
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**** fixed partition | **** fixed partition | ||
*** 1G page translations: | *** 1G page translations: | ||
− | **** 4 entries; | + | **** 4 entries; fully associative |
**** fixed partition | **** fixed partition | ||
** STLB | ** STLB | ||
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<!-- ===================== END IF YOU CHANGE HERE, CHANGE ON KABY LAKE!! ============================= --> | <!-- ===================== END IF YOU CHANGE HERE, CHANGE ON KABY LAKE!! ============================= --> | ||
+ | ==== Server ==== | ||
+ | [[File:skylake x memory changes.png|right|400px]] | ||
+ | The memory hierarchy for Skylake's server and HEDT processors has been rebalanced. Note that the L3 is now non-inclusive and some of the SRAM from the L3 cache was moved into the private L2 cache. | ||
− | * | + | * Cache |
+ | ** L2 Cache: | ||
+ | *** Unified, 1 MiB, 16-way set associative | ||
+ | *** 64 B line size | ||
+ | *** Non-inclusive | ||
+ | *** 64 B/cycle bandwidth to L1$ | ||
+ | *** Write-back policy | ||
+ | *** 14 cycles latency | ||
+ | ** L3 Cache: | ||
+ | *** 1.375 MiB/s, shared across all cores | ||
+ | **** Note that some models have non-default cache sizes which are larger due to some disabled cores | ||
+ | *** 64 B line size | ||
+ | *** 11-way set associative | ||
+ | *** Non-Inclusive | ||
+ | *** Write-back policy | ||
+ | *** 50-70 cycles latency | ||
− | == Overview == | + | == Overview (Client) == |
+ | {{main|intel/microarchitectures/skylake/Client Architecture|l1=Client Architecture}} | ||
Skylake inherits much of the {{\\|Core}} design philosophy which was enhanced significantly over the past number of architectures. Skylake, like its predecessor {{\\|Broadwell}}, is also a dual-threaded and complex [[out-of-order]] [[pipeline]]. Skylake which builds on Broadwell incorporates large number of enhancements that has improved performance and efficiency in order to cover a large spectrum of devices from ultra-low power to high-performance computing. Additionally, a large number of improvements were done to the [[integrated graphics]] and multimedia capabilities as well as a new set of security technologies were introduced. | Skylake inherits much of the {{\\|Core}} design philosophy which was enhanced significantly over the past number of architectures. Skylake, like its predecessor {{\\|Broadwell}}, is also a dual-threaded and complex [[out-of-order]] [[pipeline]]. Skylake which builds on Broadwell incorporates large number of enhancements that has improved performance and efficiency in order to cover a large spectrum of devices from ultra-low power to high-performance computing. Additionally, a large number of improvements were done to the [[integrated graphics]] and multimedia capabilities as well as a new set of security technologies were introduced. | ||
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The Skylake [[system on a chip]] consists of a five major components: CPU core, [[last level cache|LLC]], Ring interconnect, System agent, and the [[integrated graphics]]. The image shown on the right, presented by Intel at the Intel Developer Forum in 2015, represents a hypothetical model incorporating all available features Skylake has to offer (i.e. [[superset]] of features). Skylake features an improved core (see [[#Pipeline|§ Pipeline]]) with higher performance per watt and higher performance per clock. The number of cores depends on the model, but mainstream mobile models are typically [[dual-core]] while mainstream desktop models are typically [[quad-core]] with dual-core desktop models still offered for value models (e.g. {{intel|Celeron}}). Accompanying the cores is the LCC ([[last level cache]] or [[L3$]] as seen from the CPU perspective). On mainstream parts the LLC consists of 2 MiB for each core with lower amounts for value models. Connecting the cores together is the ring interconnect. The ring extends to the GPU and the system agent as well. Intel further optimized the ring in Skylake for low-power and higher bandwidth. | The Skylake [[system on a chip]] consists of a five major components: CPU core, [[last level cache|LLC]], Ring interconnect, System agent, and the [[integrated graphics]]. The image shown on the right, presented by Intel at the Intel Developer Forum in 2015, represents a hypothetical model incorporating all available features Skylake has to offer (i.e. [[superset]] of features). Skylake features an improved core (see [[#Pipeline|§ Pipeline]]) with higher performance per watt and higher performance per clock. The number of cores depends on the model, but mainstream mobile models are typically [[dual-core]] while mainstream desktop models are typically [[quad-core]] with dual-core desktop models still offered for value models (e.g. {{intel|Celeron}}). Accompanying the cores is the LCC ([[last level cache]] or [[L3$]] as seen from the CPU perspective). On mainstream parts the LLC consists of 2 MiB for each core with lower amounts for value models. Connecting the cores together is the ring interconnect. The ring extends to the GPU and the system agent as well. Intel further optimized the ring in Skylake for low-power and higher bandwidth. | ||
− | Accompanying the cores is the {{\\|Gen9}} [[integrated graphics]] unit which comes in a number of different tiers ranging from just 12 execution units (used in the ultra-low power models) all the way the GT4 ({{\\|gen9#Scalability|Gen9 § Pipeline}}) with 72 execution units boasting a peak performance of up to 2,534.4 GFLOPS (HF) / 1,267.2 GFLOPS (SP) on the highest-end workstation model. The two highest-tier models are also accompanied by dedicated [[eDRAM]] ranging from 64 to | + | Accompanying the cores is the {{\\|Gen9}} [[integrated graphics]] unit which comes in a number of different tiers ranging from just 12 execution units (used in the ultra-low power models) all the way the GT4 ({{\\|gen9#Scalability|Gen9 § Pipeline}}) with 72 execution units boasting a peak performance of up to 2,534.4 GFLOPS (HF) / 1,267.2 GFLOPS (SP) on the highest-end workstation model. The two highest-tier models are also accompanied by dedicated [[eDRAM]] ranging from 64 GiB to 120 GiB in capacity. The eDRAM is packaged along with the SoC in the same package. |
On the other side is the {{intel|System Agent}} (SA) which houses the various functionality that's not directly related to the cores or graphics. Skylake features an upgraded [[integrated memory controller]] (IMC) with most mainstream models supporting faster memory and dual-channel [[DDR4]]. The SA in Skylake also includes the [[Display Controller]] which now supports higher resolution displays with up to three displays for all mainstream models. | On the other side is the {{intel|System Agent}} (SA) which houses the various functionality that's not directly related to the cores or graphics. Skylake features an upgraded [[integrated memory controller]] (IMC) with most mainstream models supporting faster memory and dual-channel [[DDR4]]. The SA in Skylake also includes the [[Display Controller]] which now supports higher resolution displays with up to three displays for all mainstream models. | ||
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The last component of the System Agent and an entirely new addition in Skylake is the Image Processing Unit (IPU) which incorporates an [[image signal processor]] (ISP) on-die. The IPU is only available on mobile models and was added in order to improve and streamline (i.e. form factor and consistent set of features and quality) the implementation and performance of tablets and 2-in-1s. Previously this would require the assistance of an external component and the implementations varied by designer. | The last component of the System Agent and an entirely new addition in Skylake is the Image Processing Unit (IPU) which incorporates an [[image signal processor]] (ISP) on-die. The IPU is only available on mobile models and was added in order to improve and streamline (i.e. form factor and consistent set of features and quality) the implementation and performance of tablets and 2-in-1s. Previously this would require the assistance of an external component and the implementations varied by designer. | ||
− | + | == Overview (Server) == | |
− | + | {{main|intel/microarchitectures/skylake/Server Architecture|l1=Server Architecture}} | |
− | + | [[File:skylake sp (superset features).png|right|300px]] | |
− | + | Skylake-based servers have been entirely re-architected to meet the need for increased scalabiltiy and performance all while meeting power requirements. A superset model is shown on the right. Skylake-based servers are the first mainstream servers to make use of Intel's new mesh interconnect architecture, an architecture that was previously explored, experimented with, and enhanced with Intel's {{intel|Phi}} [[many-core processors]]. Those processors are offered from [[4 cores]] up to [[28 cores]] with 8 to 56 threads. With Skylake, Intel now has a separate core architecture for those chips which incorporate a plethora of new technologies and features including support for the new {{x86|AVX-512}} instruction set extension. | |
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− | + | All models incorporate 6 channels of DDR4 supporting up to 12 DIMMS for a total of 768 GiB (with extended models support 1.5 TiB). For I/O all models incorporate 48x (3x16) lanes of PCIe 3.0. There is an additional x4 lanes PCIe 3.0 reserved exclusively for DMI for the the {{intel|Lewisburg|l=chipset}} chipset. For a selected number of models (specifically those with ''F'' suffix) have an {{intel|Omni-Path}} Host Fabric Interface (HFI) on-package (see [[#Integrated_Omni-Path|Integrated Omni-Path]]). | |
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− | + | Skylake processors are designed for scalability, supporting 2-way, 4-way, and 8-way multiprocessing through Intel's new {{intel|Ultra Path Interconnect}} (UPI) interconnect links, with two to three links being offered (see [[#Scalability|§ Scalability]]). High-end models have node controller support allowing higher way (e.g., 32-way multiprocessing). | |
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== New Technologies == | == New Technologies == | ||
− | === Software Guard Extension (SGX) === | + | === Client === |
+ | ==== Software Guard Extension (SGX) ==== | ||
{{main|x86/sgx|l1=Intel's Software Guard Extension}} | {{main|x86/sgx|l1=Intel's Software Guard Extension}} | ||
'''Software Guard Extension''' ('''SGX''') is a new inter-software guard [[x86]] {{x86|extension}} that allows software in user-level mode to create isolated secure environments called "enclaves" for storing data or code. Data and code stored in enclaves are protected from external processes including code executing with higher privileges including the [[operating system]] or a [[hypervisor]] (including all forms of debugging). | '''Software Guard Extension''' ('''SGX''') is a new inter-software guard [[x86]] {{x86|extension}} that allows software in user-level mode to create isolated secure environments called "enclaves" for storing data or code. Data and code stored in enclaves are protected from external processes including code executing with higher privileges including the [[operating system]] or a [[hypervisor]] (including all forms of debugging). | ||
− | === Memory Protection Extension (MPX) === | + | ==== Memory Protection Extension (MPX) ==== |
{{main|x86/mpx|l1=Intel's Memory Protection Extension}} | {{main|x86/mpx|l1=Intel's Memory Protection Extension}} | ||
'''Memory Protection Extension''' ('''MPX''') is a new [[x86]] {{x86|extension}} that offers a hardware-level [[bound checking]] implementation. This extension allows an application to define memory boundaries for allocated memory areas. The processors can then check all proceeding memory accesses against those boundaries to ensure accesses are not [[out of bound]]. A program accessing a boundary-marked buffer out of buffer will generate an exception. | '''Memory Protection Extension''' ('''MPX''') is a new [[x86]] {{x86|extension}} that offers a hardware-level [[bound checking]] implementation. This extension allows an application to define memory boundaries for allocated memory areas. The processors can then check all proceeding memory accesses against those boundaries to ensure accesses are not [[out of bound]]. A program accessing a boundary-marked buffer out of buffer will generate an exception. | ||
+ | |||
+ | === Server === | ||
+ | In addition to the client technologies, servers have a number of new technologies as well: | ||
+ | |||
+ | ==== Key Protection Technology (KPT) ==== | ||
+ | '''Key Protection Technology''' ('''KPT''') is designed to help secure sensitive private keys in hardware at runtime. KPT augments QuickAssist Technology (QAT) hardware crypto accelerators with run-time storage of private keys using Intel's existing Platform Trust Technology (PTT), thereby allowing high throughput hardware security acceleration. The QAT accelerators are all integrated onto Intel's new {{intel|Lewisburg|l=chipsset}} chipset along with the Converged Security Manageability Engine (CSME) which implements Intel's PTT. The CSME is linked through a private hardware link that is invisible to x86 software and simple hardware probes. | ||
+ | |||
+ | ==== Memory Protection Keys for Userspace (PKU) ==== | ||
+ | '''Memory Protection Keys for Userspace''' ('''PKU''' also '''PKEY'''s) is an extension that provides a mechanism for enforcing page-based protections - all without requiring modification of the page tables when an application changes protection domains. PKU introduces 16 keys by re-purposing the 4 ignored bits from the page table entry. | ||
+ | |||
+ | ==== Mode-Based Execute (MBE) Control ==== | ||
+ | '''Mode-Based Execute''' ('''MBE''') is an enhancement to the Extended Page Tables (EPT) that provides finer level of control of execute permissions. With MBE the previous Execute Enable (''X'') bit is turned into Excuse Userspace page (XU) and Execute Supervisor page (XS). The processor selects the mode based on the guest page permission. With proper software support, hypervisors can take advantage of this as well to ensure integrity of kernel-level code. | ||
== Power == | == Power == | ||
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Prior to Skylake, SpeedStep had three major domains: [[Cores]], [[Integrated Graphics]], and Coherent Fabric. With Skylake, SpeedStep has been extended to a number of new domains, including the [[System Agent]], Memory, and the [[eDRAM]] I/O. Depending on the bandwidth consumption, SpeedStep can now save energy by reducing frequency on the new domains. | Prior to Skylake, SpeedStep had three major domains: [[Cores]], [[Integrated Graphics]], and Coherent Fabric. With Skylake, SpeedStep has been extended to a number of new domains, including the [[System Agent]], Memory, and the [[eDRAM]] I/O. Depending on the bandwidth consumption, SpeedStep can now save energy by reducing frequency on the new domains. | ||
− | Information from the new domains, including additional thermal | + | Information from the new domains, including additional thermal skin temperature control information is now supplied to OEMs. |
==== Power of System (Psys) ==== | ==== Power of System (Psys) ==== | ||
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</table> | </table> | ||
− | Note that core ratio has been increased to a [theoretical] x83 multiplier and the coarse-grain ratio was dropped from Skylake allowing a BCLK ratio to have granularity of 1 MHz increments with BCLK frequency of over 200 readily achievable. The | + | Note that core ratio has been increased to a [theoretical] x83 multiplier and the coarse-grain ratio was dropped from Skylake allowing a BCLK ratio to have granularity of 1 MHz increments with BCLK frequency of over 200 readily achievable. The FIVER was removed and the voltage control was given back to the motherboard manufacturers; i.e., voltage supplies can be entirely motherboard-controlled. Skylake also bumped the DDR ratio up to 4133 MT/s. |
[[File:skylake bclk.png|left|300px]] | [[File:skylake bclk.png|left|300px]] | ||
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The IPU hardware supports: | The IPU hardware supports: | ||
− | + | * 13 [[megapixel|MP]] zero [[shutter lag]] 1080p60/2160p30 video capture and imaging and a large array of standardized image processing capabilities. | |
− | |||
* Face detection and recognition (smile/blink/group setting) | * Face detection and recognition (smile/blink/group setting) | ||
* Full resolution still capture during video captures | * Full resolution still capture during video captures | ||
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| Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux | | Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux | ||
|- | |- | ||
− | | {{intel|HD Graphics 510}} || 12 || GT1 || {{intel|Skylake U|U|l=core}}, {{intel|Skylake S|S|l=core}} || - || rowspan=" | + | | {{intel|HD Graphics 510}} || 12 || GT1 || {{intel|Skylake U|U|l=core}}, {{intel|Skylake S|S|l=core}} || - || rowspan="11" colspan="2" style="text-align: center;" | '''1.0''' || rowspan="11" style="text-align: center;" | '''12''' || rowspan="11" style="text-align: center;" | '''N/A''' || rowspan="11" style="text-align: center;" | '''5.1''' || rowspan="11" style="text-align: center;" | '''4.5''' || rowspan="11" style="text-align: center;" | '''4.5''' || rowspan="11" style="text-align: center;" colspan="2" | '''2.0''' |
|- | |- | ||
| {{intel|HD Graphics 515}} || 24 || GT2 || {{intel|Skylake Y|Y|l=core}} || - | | {{intel|HD Graphics 515}} || 24 || GT2 || {{intel|Skylake Y|Y|l=core}} || - | ||
Line 777: | Line 708: | ||
| [[File:skylake u (back; standard).png|100px|link=intel/cores/skylake_u]] || {{intel|Skylake U|l=core}} || {{intel|BGA-1356}} || Yes || 1-chip | | [[File:skylake u (back; standard).png|100px|link=intel/cores/skylake_u]] || {{intel|Skylake U|l=core}} || {{intel|BGA-1356}} || Yes || 1-chip | ||
|- | |- | ||
− | | [[File:skylake h (back).png|100px|link=intel/cores/skylake_h]] || {{intel|Skylake H|l=core}} || {{intel|BGA-1440}} || Yes || 2-chip || rowspan="2" | {{intel|Sunrise Point}} || rowspan=" | + | | [[File:skylake h (back).png|100px|link=intel/cores/skylake_h]] || {{intel|Skylake H|l=core}} || {{intel|BGA-1440}} || Yes || 2-chip || rowspan="2" | {{intel|Sunrise Point}} || rowspan="4" | [[DMI 3.0]] |
|- | |- | ||
| rowspan="2" | [[File:skylake s (back).png|100px|link=intel/cores/skylake_s]] || {{intel|Skylake S|l=core}} || {{intel|LGA-1151}} || No || 2-chip | | rowspan="2" | [[File:skylake s (back).png|100px|link=intel/cores/skylake_s]] || {{intel|Skylake S|l=core}} || {{intel|LGA-1151}} || No || 2-chip | ||
|- | |- | ||
| {{intel|Skylake DT|l=core}} || {{intel|LGA-1151}} || No || 2-chip || Xeon {{intel|Sunrise Point}} | | {{intel|Skylake DT|l=core}} || {{intel|LGA-1151}} || No || 2-chip || Xeon {{intel|Sunrise Point}} | ||
+ | |- | ||
+ | | [[File:skylake x (back).png|100px|link=intel/cores/skylake_x]] || {{intel|Skylake X|l=core}} || {{intel|LGA-2066}} || No || 2-chip || {{intel|Lewisburg}} | ||
|} | |} | ||
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== Die == | == Die == | ||
− | + | === Client Die === | |
Skylake desktop and mobile come and [[2 cores|2]] and [[4 cores|4]] cores. Each variant has its own die. One of the most noticeable changes on die is the amount of die space allocated to the [[GPU]]. The major components of the die is: | Skylake desktop and mobile come and [[2 cores|2]] and [[4 cores|4]] cores. Each variant has its own die. One of the most noticeable changes on die is the amount of die space allocated to the [[GPU]]. The major components of the die is: | ||
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* Memory Controller | * Memory Controller | ||
− | === System Agent === | + | ==== System Agent ==== |
The System Agent (SA) contains the Image Processing Unit (IPU), the Display Engine (DE), the I/O bus and various other shared functionality. Note that the mainstream desktop (i.e., [[quad-core]] die) does not have an IPU (The memory controller actually occupies a portion of where it would otherwise be). | The System Agent (SA) contains the Image Processing Unit (IPU), the Display Engine (DE), the I/O bus and various other shared functionality. Note that the mainstream desktop (i.e., [[quad-core]] die) does not have an IPU (The memory controller actually occupies a portion of where it would otherwise be). | ||
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{{clear}} | {{clear}} | ||
− | === Core === | + | ==== Core ==== |
Skylake Client models come in either 2x core or 4x core setup. | Skylake Client models come in either 2x core or 4x core setup. | ||
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: [[File:skylake core die (annotated).png|450px]] | : [[File:skylake core die (annotated).png|450px]] | ||
− | === Core Group === | + | ==== Core Group ==== |
− | Client models come in groups of 2 or 4 cores. (die sizes includes the | + | Client models come in groups of 2 or 4 cores. (die sizes includes the dark silicon space where the L3 ends). |
* 2-cores group: | * 2-cores group: | ||
− | + | * ~8.91 mm x ~2.845 mm | |
− | + | * ~25.347 mm² | |
: [[File:skylake 2x core complex die.png|500px]] | : [[File:skylake 2x core complex die.png|500px]] | ||
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* 4-core group | * 4-core group | ||
− | + | * ~8.844 mm x 5.694 mm | |
− | + | * ~50.354 mm² | |
: [[File:skylake 4x core complex die.png|500px]] | : [[File:skylake 4x core complex die.png|500px]] | ||
− | === Integrated Graphics === | + | |
+ | ==== Integrated Graphics ==== | ||
The [[integrated graphics]] takes up the largest portion of the die. The normal [[dual-core]] and [[quad-core]] dies come with 24 EU {{\\|Gen9.5}} GPU (with 12 units disabled on the low end models). | The [[integrated graphics]] takes up the largest portion of the die. The normal [[dual-core]] and [[quad-core]] dies come with 24 EU {{\\|Gen9.5}} GPU (with 12 units disabled on the low end models). | ||
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{{clear}} | {{clear}} | ||
− | === Dual-core === | + | ==== Dual-core ==== |
Die shot of the [[dual-core]] {{\\|Gen9|GT2}} Skylake processors. Those are found in mobile models, and entry-level/budget processors: | Die shot of the [[dual-core]] {{\\|Gen9|GT2}} Skylake processors. Those are found in mobile models, and entry-level/budget processors: | ||
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* 11 metal layers | * 11 metal layers | ||
* ~1,750,000,000 transistors | * ~1,750,000,000 transistors | ||
− | * ~9. | + | * ~9.57 mm x ~10.3 mm |
− | * ~ | + | * ~98.57 mm² die size |
* 2 CPU cores + 24 GPU EUs | * 2 CPU cores + 24 GPU EUs | ||
Line 874: | Line 808: | ||
: [[File:skylake (dual core) (annotated).png|650px]] | : [[File:skylake (dual core) (annotated).png|650px]] | ||
− | === Quad-core === | + | ==== Quad-core ==== |
− | Die shot of the [[quad-core]] {{\\|Gen9|GT2}} | + | Die shot of the [[quad-core]] {{\\|Gen9|GT2}} Skyllake processors. Those are found in almost all mainstream desktop processors. |
* [[14 nm process]] | * [[14 nm process]] | ||
* 11 metal layers | * 11 metal layers | ||
− | + | * ~122 mm² die size | |
− | * ~122 | ||
* 4 CPU cores + 24 GPU EUs | * 4 CPU cores + 24 GPU EUs | ||
− | : [[File:skylake (quad-core).png | + | : [[File:skylake (quad-core).png|650px]] |
: [[File:skylake (quad-core) (annotated).png|650px]] | : [[File:skylake (quad-core) (annotated).png|650px]] | ||
+ | |||
+ | === Server Die === | ||
+ | [[File:intel xeon skylake sp.jpg|right|300px|thumb|Skylake SP chips and wafer.]] | ||
+ | Skylake Server class models and high-end desktop (HEDT) consist of 3 different dies: Low Core Count (LCC), High Core Count (HCC), and Extreme Core Count (XCC). | ||
+ | |||
+ | ==== Low Core Count (LCC) ==== | ||
+ | * [[14 nm process]] | ||
+ | * ? metal layers | ||
+ | * ~22.26 mm x ~14.62 mm | ||
+ | * ~325.44 mm² die size | ||
+ | * [[10 cores]] | ||
+ | |||
+ | ==== High Core Count (HCC) ==== | ||
+ | Die shot of the [[octadeca core]] HEDT {{intel|Skylake X|l=core}} processors. | ||
+ | |||
+ | * [[14 nm process]] | ||
+ | * ? metal layers | ||
+ | * ? mm² die size | ||
+ | * [[18 cores]] | ||
+ | |||
+ | |||
+ | : [[File:skylake (octadeca core).png|650px]] | ||
+ | |||
+ | {{future information}} | ||
+ | |||
+ | |||
+ | : [[File:skylake (octadeca core) (annotated).png|650px]] | ||
+ | |||
+ | ==== Extreme Core Count (XCC) ==== | ||
+ | * [[14 nm process]] | ||
+ | * ? metal layers | ||
+ | * ? mm² die size | ||
+ | * [[28 cores]] | ||
+ | |||
+ | : [[File:skylake-sp hcc die shot.png|650px]] | ||
+ | |||
+ | |||
+ | {{future information}} | ||
+ | |||
+ | |||
+ | : [[File:skylake-sp hcc die shot (annotated).png|650px]] | ||
== All Skylake Chips == | == All Skylake Chips == | ||
Line 938: | Line 912: | ||
|limit=200 | |limit=200 | ||
}} | }} | ||
− | {{ | + | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Multiprocessors]] (2-way)</th></tr> |
+ | {{#ask: | ||
+ | [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Skylake]] [[max cpu count::2]] | ||
+ | |?full page name | ||
+ | |?model number | ||
+ | |?first launched | ||
+ | |?release price | ||
+ | |?microprocessor family | ||
+ | |?core name | ||
+ | |?core count | ||
+ | |?thread count | ||
+ | |?l2$ size | ||
+ | |?l3$ size | ||
+ | |?tdp | ||
+ | |?base frequency#GHz | ||
+ | |?turbo frequency (1 core)#GHz | ||
+ | |?turbo frequency (2 cores)#GHz | ||
+ | |?turbo frequency (3 cores)#GHz | ||
+ | |?turbo frequency (4 cores)#GHz | ||
+ | |?max memory#GiB | ||
+ | |?integrated gpu | ||
+ | |?integrated gpu base frequency | ||
+ | |?integrated gpu max frequency | ||
+ | |?has intel turbo boost technology 2_0 | ||
+ | |?has simultaneous multithreading | ||
+ | |?has advanced vector extensions 2 | ||
+ | |?has intel trusted execution technology | ||
+ | |?has transactional synchronization extensions | ||
+ | |?has intel vpro technology | ||
+ | |format=template | ||
+ | |template=proc table 3 | ||
+ | |searchlabel= | ||
+ | |sort=microprocessor family, model number | ||
+ | |order=asc,asc | ||
+ | |userparam=26:21 | ||
+ | |mainlabel=- | ||
+ | |limit=60 | ||
+ | }} | ||
+ | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Multiprocessors]] (4-way)</th></tr> | ||
+ | {{#ask: | ||
+ | [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Skylake]] [[max cpu count::4]] | ||
+ | |?full page name | ||
+ | |?model number | ||
+ | |?first launched | ||
+ | |?release price | ||
+ | |?microprocessor family | ||
+ | |?core name | ||
+ | |?core count | ||
+ | |?thread count | ||
+ | |?l2$ size | ||
+ | |?l3$ size | ||
+ | |?tdp | ||
+ | |?base frequency#GHz | ||
+ | |?turbo frequency (1 core)#GHz | ||
+ | |?turbo frequency (2 cores)#GHz | ||
+ | |?turbo frequency (3 cores)#GHz | ||
+ | |?turbo frequency (4 cores)#GHz | ||
+ | |?max memory#GiB | ||
+ | |?integrated gpu | ||
+ | |?integrated gpu base frequency | ||
+ | |?integrated gpu max frequency | ||
+ | |?has intel turbo boost technology 2_0 | ||
+ | |?has simultaneous multithreading | ||
+ | |?has advanced vector extensions 2 | ||
+ | |?has intel trusted execution technology | ||
+ | |?has transactional synchronization extensions | ||
+ | |?has intel vpro technology | ||
+ | |format=template | ||
+ | |template=proc table 3 | ||
+ | |searchlabel= | ||
+ | |sort=microprocessor family, model number | ||
+ | |order=asc,asc | ||
+ | |userparam=26:21 | ||
+ | |mainlabel=- | ||
+ | |limit=60 | ||
+ | }} | ||
+ | <tr class="comptable-header comptable-header-sep"><th> </th><th colspan="25">[[Multiprocessors]] (8-way)</th></tr> | ||
+ | {{#ask: | ||
+ | [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Skylake]] [[max cpu count::8]] | ||
+ | |?full page name | ||
+ | |?model number | ||
+ | |?first launched | ||
+ | |?release price | ||
+ | |?microprocessor family | ||
+ | |?core name | ||
+ | |?core count | ||
+ | |?thread count | ||
+ | |?l2$ size | ||
+ | |?l3$ size | ||
+ | |?tdp | ||
+ | |?base frequency#GHz | ||
+ | |?turbo frequency (1 core)#GHz | ||
+ | |?turbo frequency (2 cores)#GHz | ||
+ | |?turbo frequency (3 cores)#GHz | ||
+ | |?turbo frequency (4 cores)#GHz | ||
+ | |?max memory#GiB | ||
+ | |?integrated gpu | ||
+ | |?integrated gpu base frequency | ||
+ | |?integrated gpu max frequency | ||
+ | |?has intel turbo boost technology 2_0 | ||
+ | |?has simultaneous multithreading | ||
+ | |?has advanced vector extensions 2 | ||
+ | |?has intel trusted execution technology | ||
+ | |?has transactional synchronization extensions | ||
+ | |?has intel vpro technology | ||
+ | |format=template | ||
+ | |template=proc table 3 | ||
+ | |searchlabel= | ||
+ | |sort=microprocessor family, model number | ||
+ | |order=asc,asc | ||
+ | |userparam=26:21 | ||
+ | |mainlabel=- | ||
+ | |limit=60 | ||
+ | }} | ||
+ | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Skylake]]}} | ||
</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
Line 957: | Line 1,045: | ||
* [[:File:6th Gen Intel® Core™ vPro™ Processor Family Product Brief.pdf|6th Gen Intel® Core™ vPro™ Processor Family Product Brief]] | * [[:File:6th Gen Intel® Core™ vPro™ Processor Family Product Brief.pdf|6th Gen Intel® Core™ vPro™ Processor Family Product Brief]] | ||
* [[:File:6th Generation Intel® Core™ Desktop Processors i7-6700K and i5-6600K Product Brief.pdf|6th Generation Intel® Core™ Desktop Processors i7-6700K and i5-6600K Product Brief]] | * [[:File:6th Generation Intel® Core™ Desktop Processors i7-6700K and i5-6600K Product Brief.pdf|6th Generation Intel® Core™ Desktop Processors i7-6700K and i5-6600K Product Brief]] | ||
+ | * [[:File:Intel-Core-X-Series-Processor-Family Product-Information.pdf|New Intel Core X-Series Processor Family]] | ||
+ | * [[:File:intel-xeon-scalable-processors-product-brief.pdf|Intel Xeon (Skylake SP) Processors Product Brief]] | ||
+ | * [[:File:intel-xeon-scalable-processors-overview.pdf|Intel Xeon (Skylake SP) Processors Product Overview]] | ||
Facts about "Skylake (client) - Microarchitectures - Intel"
codename | Skylake (client) + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | August 5, 2015 + |
full page name | intel/microarchitectures/skylake (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Skylake (client) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |