Semiconductor & Computer Engineering
From WikiChip
Editing intel/microarchitectures/palm cove
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
| Latest revision | Your text | ||
| Line 7: | Line 7: | ||
|introduction=2018 | |introduction=2018 | ||
|process=10 nm | |process=10 nm | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
|isa=x86-64 | |isa=x86-64 | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
|predecessor=Skylake | |predecessor=Skylake | ||
|predecessor link=intel/microarchitectures/skylake | |predecessor link=intel/microarchitectures/skylake | ||
| Line 71: | Line 21: | ||
=== Key changes from {{\\|Skylake (Client)}}=== | === Key changes from {{\\|Skylake (Client)}}=== | ||
* [[10 nm process]] (From [[14 nm]]) | * [[10 nm process]] (From [[14 nm]]) | ||
| − | * | + | * Core |
| − | |||
| − | |||
| − | |||
** Execution units | ** Execution units | ||
| − | + | *** New 512-bit FMA unit | |
| − | *** New | ||
*** New iDIV unit | *** New iDIV unit | ||
| − | |||
| − | |||
| − | |||
| − | |||
{{expand list}} | {{expand list}} | ||
Facts about "Palm Cove - Microarchitectures - Intel"
| codename | Palm Cove + |
| core count | 2 + |
| designer | Intel + |
| first launched | 2018 + |
| full page name | intel/microarchitectures/palm cove + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Palm Cove + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |
