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== Architecture == | == Architecture == | ||
| − | === Key changes from {{\\|Skylake ( | + | === Key changes from {{\\|Skylake (Server)}}=== |
* [[10 nm process]] (From [[14 nm]]) | * [[10 nm process]] (From [[14 nm]]) | ||
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{{expand list}} | {{expand list}} | ||
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* {{x86|SHA|<code>SHA</code>}} - [[Hardware acceleration]] for SHA hashing operations | * {{x86|SHA|<code>SHA</code>}} - [[Hardware acceleration]] for SHA hashing operations | ||
* {{x86|UMIP|<code>UMIP</code>}} - User-Mode Instruction Prevention extension | * {{x86|UMIP|<code>UMIP</code>}} - User-Mode Instruction Prevention extension | ||
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== Overview == | == Overview == | ||
Facts about "Palm Cove - Microarchitectures - Intel"
| codename | Palm Cove + |
| core count | 2 + |
| designer | Intel + |
| first launched | 2018 + |
| full page name | intel/microarchitectures/palm cove + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Palm Cove + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |
