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:[[File:ice lake io subsystem.svg|center|800px]] | :[[File:ice lake io subsystem.svg|center|800px]] | ||
− | {{center| | + | {{center|Ice Lake Thunderbolt 3 I/O Subsystem}} |
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:[[File:intel type-c old.svg|center|500px]] | :[[File:intel type-c old.svg|center|500px]] | ||
− | {{center| | + | {{center|Thunderbolt 3 support using the Titan Ridge controller.}} |
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:[[File:intel type-c ice lake.svg|center|700px]] | :[[File:intel type-c ice lake.svg|center|700px]] | ||
− | {{center| | + | {{center|Thunderbolt 3 support on Ice Lake through the Thunderbolt 3 integration}} |
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:[[File:intel type-c ice lake 4p.svg|center|700px]] | :[[File:intel type-c ice lake 4p.svg|center|700px]] | ||
− | {{center| | + | {{center|Thunderbolt 3 support on Ice Lake through the Thunderbolt 3 integration<br>Full configuration with four ports and every feature through every port}} |
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== Clock domains == | == Clock domains == |
Facts about "Ice Lake (client) - Microarchitectures - Intel"
codename | Ice Lake (client) + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | May 27, 2019 + |
full page name | intel/microarchitectures/ice lake (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Ice Lake (client) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |