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Ice Lake is divided into a number of [[clock domains]], each controlling the clock frequency of their respective unit in the processor. All clock domains are some multiple of the [virtual] bus clock ([[BCLK]]). | Ice Lake is divided into a number of [[clock domains]], each controlling the clock frequency of their respective unit in the processor. All clock domains are some multiple of the [virtual] bus clock ([[BCLK]]). | ||
| − | * '''BCLK''' - Bus/Base Clock - The system bus interface frequency (once upon a time referred to the actual [[FSB]] speed, it now serves as only a base clock reference for all other clock domains). The base clock is 100 MHz. | + | * '''BCLK''' - Bus/Base Clock - The system bus interface frequency (once upon a time referred to the actual [[FSB]] speed, it now serves as only a base clock reference for all other clock domains). The base clock is 100 MHz. |
* '''Core Clock''' - The frequency at which the core and the [[L1]]/[[L2]] caches operate at. (Frequency depends on the model and is represented as a multiple of BCLK). | * '''Core Clock''' - The frequency at which the core and the [[L1]]/[[L2]] caches operate at. (Frequency depends on the model and is represented as a multiple of BCLK). | ||
* '''Ring Clock''' - The frequency at which the ring interconnect and [[L3$|LLC]] operate at. Data from/to the individual cores are read/written into the L3 at a rate of 32B/cycle operating at Ring Clock frequency. | * '''Ring Clock''' - The frequency at which the ring interconnect and [[L3$|LLC]] operate at. Data from/to the individual cores are read/written into the L3 at a rate of 32B/cycle operating at Ring Clock frequency. | ||
| − | * '''IGP Clock''' - The frequency at which the [[integrated graphics]] ({{\\| | + | * '''IGP Clock''' - The frequency at which the [[integrated graphics]] ({{\\|Gen9}} GPU) operates at. Data from/to the GPU are read/written into the LLC at a rate of 64B/cycle operating at this frequency as well. |
* '''IPU''' - The frequency at which the [[image processing unit]] operates at | * '''IPU''' - The frequency at which the [[image processing unit]] operates at | ||
| − | * '''MemClk''' - Memory Clock - The frequency at which the system DRAM operates at. DRAM data is | + | * '''MemClk''' - Memory Clock - The frequency at which the system DRAM operates at. DRAM data is transfered at a rate of 8B/cycle operating at MemClk frequency. |
[[File:ice lake soc clock domain block diagram.svg|850px]] | [[File:ice lake soc clock domain block diagram.svg|850px]] | ||
Facts about "Ice Lake (client) - Microarchitectures - Intel"
| codename | Ice Lake (client) + |
| core count | 2 + and 4 + |
| designer | Intel + |
| first launched | May 27, 2019 + |
| full page name | intel/microarchitectures/ice lake (client) + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Ice Lake (client) + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |
