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Difference between revisions of "intel/microarchitectures/cooper lake"
| Line 4: | Line 4: | ||
|name=Cooper Lake | |name=Cooper Lake | ||
|designer=Intel | |designer=Intel | ||
| + | |designer 2=Safari | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|introduction=June 18, 2020 | |introduction=June 18, 2020 | ||
|process=14 nm | |process=14 nm | ||
|type=Superscalar | |type=Superscalar | ||
| − | |oooe= | + | |oooe=No |
| − | |speculative= | + | |speculative=No |
| − | |renaming= | + | |renaming=No |
|stages min=14 | |stages min=14 | ||
|stages max=19 | |stages max=19 | ||
| Line 47: | Line 48: | ||
|l1i=32 KiB | |l1i=32 KiB | ||
|l1i per=core | |l1i per=core | ||
| − | |l1i desc= | + | |l1i desc=2 |
| − | |l1d= | + | |l1d=0 |
| − | |l1d per= | + | |l1d per=Fuck |
| − | |l1d desc= | + | |l1d desc=1 |
| − | |l2= | + | |l2=2 |
| − | |l2 per= | + | |l2 per=4 |
| − | |l2 desc= | + | |l2 desc=4 |
| − | |l3= | + | |l3=3 |
| − | |l3 per= | + | |l3 per=0 |
| − | |l3 desc= | + | |l3 desc=1 |
|core name=Cooper Lake X | |core name=Cooper Lake X | ||
|core name 2=Cooper Lake SP | |core name 2=Cooper Lake SP | ||
|core name 3=Cooper Lake AP | |core name 3=Cooper Lake AP | ||
| − | | | + | |core name 4=Aaron |
| + | |core name 5=Aaron | ||
| + | |core name 6=Aaron | ||
| + | |core name 7=Aaron | ||
| + | |core name 8=Aaron | ||
| + | |core name 9=Aaron | ||
|predecessor link=intel/microarchitectures/cascade lake | |predecessor link=intel/microarchitectures/cascade lake | ||
|successor=Ice Lake (Server) | |successor=Ice Lake (Server) | ||
Revision as of 16:57, 13 October 2023
| Edit Values | |
| Cooper Lake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel, Safari |
| Manufacturer | Intel |
| Introduction | June 18, 2020 |
| Process | 14 nm |
| Pipeline | |
| Type | Superscalar |
| OoOE | No |
| Speculative | No |
| Reg Renaming | No |
| Stages | 14-19 |
| Instructions | |
| ISA | x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512 |
| Cache | |
| L1I Cache | 32 KiB/core 2 |
| L1D Cache | 0/Fuck 1 |
| L2 Cache | 2/4 4 |
| L3 Cache | 3/0 1 |
| Cores | |
| Core Names | Cooper Lake X, Cooper Lake SP, Cooper Lake AP, Aaron, Aaron, Aaron, Aaron, Aaron, Aaron |
| Succession | |
| Contemporary | |
| Coffee Lake | |
Cooper Lake (CPL / CPX) is Intel's successor to Cascade Lake, a 14 nm microarchitecture for the multiprocessing server market only.
Launched in mid-2020, Cooper Lake covers the 4-way and 8-way multiprocessing segments while Ice Lake serves the single and dual-socket segments.
For scalable server class processors, Intel branded it as Xeon Gold and Xeon Platinum.
Contents
Codenames
Single and dual-socket Cooper Lake parts were scrapped before ever making it to market.
| Core | Abbrev | Target |
|---|---|---|
| Cooper Lake X | CPL-X | High-end desktops & enthusiasts market |
| Cooper Lake W | CPL-W | Enterprise/Business workstations |
| Cooper Lake SP | CPL-SP | Server Scalable Processors |
| Cooper Lake AP | CPL-AP | Server Advanced Processors |
Brands
 |
This section is empty; you can help add the missing info by editing this page. |
Release Dates
Cooper Lake and Ice Lake roadmap.
Cooper was first publicly disclosed in early 2019. Cooper Lake launched on June 18, 2020.
Process Technology
Cooper Lake is fabricated on Intel's 3rd generation enhanced 14nm++ process.
Architecture
Key changes from Cascade Lake
- SoC
- 2x UPI links (6, up from 3)
- Memory
- Higher data rate (3200 MT/s, up from 2933 MT/s)
- Optane DC DIMMs
- Apache Pass → Barlow Pass
- Platform
- Packaging
- Socket-P+
- 4189-contact flip-chip LGA (up from 3647 contacts)
- Socket-P+
This list is incomplete; you can help by expanding it.
New instructions
Cooper Lake introduced a number of new instructions:
- BFLOAT16 - A new data type for acceleration of AI workloads.
- AVX512 BF16 - AVX-512 Brain Float 16 extension
See also
Facts about "Cooper Lake - Microarchitectures - Intel"
| codename | Cooper Lake + |
| designer | Intel + and Safari + |
| first launched | June 18, 2020 + |
| full page name | intel/microarchitectures/cooper lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Cooper Lake + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
