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| {{intel|Cascade Lake W|l=core}} || CSL-W || || Enterprise/Business workstations | | {{intel|Cascade Lake W|l=core}} || CSL-W || || Enterprise/Business workstations | ||
|- | |- | ||
− | | {{intel|Cascade Lake SP|l=core}} || | + | | {{intel|Cascade Lake SP|l=core}} || CSL-SP || || Server Scalable Processors |
|- | |- | ||
− | | {{intel|Cascade Lake AP|l=core}} || | + | | {{intel|Cascade Lake AP|l=core}} || CSL-AP || || Server Advanced Processors |
|} | |} | ||
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===== LCC SoC ===== | ===== LCC SoC ===== | ||
:[[File:skylake sp lcc block diagram.svg|500px]] | :[[File:skylake sp lcc block diagram.svg|500px]] | ||
− | |||
===== HCC SoC ===== | ===== HCC SoC ===== | ||
:[[File:skylake sp hcc block diagram.svg|600px]] | :[[File:skylake sp hcc block diagram.svg|600px]] | ||
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===== Individual Core ===== | ===== Individual Core ===== | ||
<small>The high-level core architecture is identical to that of {{\\|Skylake (server)#Individual Core|Skylake}}.</small> | <small>The high-level core architecture is identical to that of {{\\|Skylake (server)#Individual Core|Skylake}}.</small> | ||
− | :[[File:skylake server block diagram.svg| | + | :[[File:skylake server block diagram.svg|950px]] |
=== Memory Hierarchy === | === Memory Hierarchy === | ||
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*** 2,048 sets, 12-way set associative | *** 2,048 sets, 12-way set associative | ||
* DRAM | * DRAM | ||
− | ** 6 channels of DDR4, up to | + | ** 6 channels of DDR4, up to 2666 MT/s |
*** RDIMM and LRDIMM | *** RDIMM and LRDIMM | ||
− | *** bandwidth of | + | *** bandwidth of 21.33 GB/s |
− | *** aggregated bandwidth of | + | *** aggregated bandwidth of 128 GB/s |
Cascade Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). | Cascade Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). |
Facts about "Cascade Lake - Microarchitectures - Intel"
codename | Cascade Lake + |
core count | 2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 +, 28 +, 32 +, 48 + and 56 + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/cascade lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cascade Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |