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| {{intel|Cascade Lake W|l=core}} || CSL-W || || Enterprise/Business workstations | | {{intel|Cascade Lake W|l=core}} || CSL-W || || Enterprise/Business workstations | ||
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− | | {{intel|Cascade Lake SP|l=core}} || | + | | {{intel|Cascade Lake SP|l=core}} || CSL-SP || || Server Scalable Processors |
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− | | {{intel|Cascade Lake AP|l=core}} || | + | | {{intel|Cascade Lake AP|l=core}} || CSL-AP || || Server Advanced Processors |
|} | |} | ||
== Brands == | == Brands == | ||
− | Cascade Lake is sold under | + | Cascade Lake is sold under four different families. |
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | ||
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! Cores !! {{intel|Hyper-Threading|HT}} !! {{intel|Turbo Boost|TBT}} !! {{x86|AVX-512}} !! AVX-512 Units !! {{intel|Ultra Path Interconnect|UPI}} links !! Scalability | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{intel|Turbo Boost|TBT}} !! {{x86|AVX-512}} !! AVX-512 Units !! {{intel|Ultra Path Interconnect|UPI}} links !! Scalability | ||
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| [[File:xeon bronze (2017).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || 6 || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}} || 1 || 2 || Up to 2 | | [[File:xeon bronze (2017).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || 6 || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}} || 1 || 2 || Up to 2 | ||
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== Release Dates == | == Release Dates == | ||
− | Cascade Lake was released on April 2 | + | Cascade Lake was released on April 2, 2019. |
== Process Technology == | == Process Technology == | ||
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===== LCC SoC ===== | ===== LCC SoC ===== | ||
:[[File:skylake sp lcc block diagram.svg|500px]] | :[[File:skylake sp lcc block diagram.svg|500px]] | ||
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===== HCC SoC ===== | ===== HCC SoC ===== | ||
:[[File:skylake sp hcc block diagram.svg|600px]] | :[[File:skylake sp hcc block diagram.svg|600px]] | ||
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===== Individual Core ===== | ===== Individual Core ===== | ||
<small>The high-level core architecture is identical to that of {{\\|Skylake (server)#Individual Core|Skylake}}.</small> | <small>The high-level core architecture is identical to that of {{\\|Skylake (server)#Individual Core|Skylake}}.</small> | ||
− | :[[File:skylake server block diagram.svg| | + | :[[File:skylake server block diagram.svg|950px]] |
=== Memory Hierarchy === | === Memory Hierarchy === | ||
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*** 2,048 sets, 12-way set associative | *** 2,048 sets, 12-way set associative | ||
* DRAM | * DRAM | ||
− | ** 6 channels of DDR4, up to | + | ** 6 channels of DDR4, up to 2666 MT/s |
*** RDIMM and LRDIMM | *** RDIMM and LRDIMM | ||
− | *** bandwidth of | + | *** bandwidth of 21.33 GB/s |
− | *** aggregated bandwidth of | + | *** aggregated bandwidth of 128 GB/s |
Cascade Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). | Cascade Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). | ||
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{{main|intel/speed select technology|l1=Speed Select Technology}} | {{main|intel/speed select technology|l1=Speed Select Technology}} | ||
One of the other features that was added in Cascade Lake is Speed Select Technology (SST) which allows a chip to be configured in the field for various workloads such as throughput and single-core performance. This is done through configurations that allow the end user to determine how the power budget is spent. For example, single-thread performance can be further increased for fewer chips by further decreasing the base frequency of more inactive core. Alternatively, higher throughput can be achieved by increasing the base frequency of some cores while reducing the base frequency of other cores. All in all, the conigurations are ultimately bound by the power budget of the chip, however the custom tweaking of frquency (base, turbo, or otherwise) enable custom tuning of affinitized workloads. | One of the other features that was added in Cascade Lake is Speed Select Technology (SST) which allows a chip to be configured in the field for various workloads such as throughput and single-core performance. This is done through configurations that allow the end user to determine how the power budget is spent. For example, single-thread performance can be further increased for fewer chips by further decreasing the base frequency of more inactive core. Alternatively, higher throughput can be achieved by increasing the base frequency of some cores while reducing the base frequency of other cores. All in all, the conigurations are ultimately bound by the power budget of the chip, however the custom tweaking of frquency (base, turbo, or otherwise) enable custom tuning of affinitized workloads. | ||
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== Persistent memory support == | == Persistent memory support == | ||
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Although the instructions to support persistent memory were already introduced in {{\\|Skylake (Server)|Skylake}}, Cascade Lake can now actually make use of them. The bare minimum for persistent memory support can be realized by simply putting the data in the write pending queue (WPQ) of the integrated memory controller within the persistence domain. The persistence domain is a unique checkpoint. Once data makes it to that point, it’s persistence is guaranteed by the platform interface. This is shown in the diagram on the right in the bottom dotted box. Any data within that box is either saved on the DIMM, on the way to the DIMM, or in the WPQ in the IMC. Regardless of where it is, the platform is required to store enough energy (e.g., through on-board supercapacitors) to save everything within that box in the event of a power loss. | Although the instructions to support persistent memory were already introduced in {{\\|Skylake (Server)|Skylake}}, Cascade Lake can now actually make use of them. The bare minimum for persistent memory support can be realized by simply putting the data in the write pending queue (WPQ) of the integrated memory controller within the persistence domain. The persistence domain is a unique checkpoint. Once data makes it to that point, it’s persistence is guaranteed by the platform interface. This is shown in the diagram on the right in the bottom dotted box. Any data within that box is either saved on the DIMM, on the way to the DIMM, or in the WPQ in the IMC. Regardless of where it is, the platform is required to store enough energy (e.g., through on-board supercapacitors) to save everything within that box in the event of a power loss. | ||
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== Scalability == | == Scalability == |
Facts about "Cascade Lake - Microarchitectures - Intel"
codename | Cascade Lake + |
core count | 2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 +, 28 +, 32 +, 48 + and 56 + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/cascade lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cascade Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |