From WikiChip
Editing intel/microarchitectures/cascade lake
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 83: | Line 83: | ||
|contemporary link=intel/microarchitectures/coffee lake | |contemporary link=intel/microarchitectures/coffee lake | ||
}} | }} | ||
− | |||
'''Cascade Lake''' ('''CSL'''/'''CLX''') is [[Intel]]'s successor to {{\\|Skylake (server)|Skylake}}, a [[14 nm]] [[microarchitecture]] for enthusiasts and servers. Cascade Lake is the "Optimization" phase as part of Intel's {{intel|PAO}} model. | '''Cascade Lake''' ('''CSL'''/'''CLX''') is [[Intel]]'s successor to {{\\|Skylake (server)|Skylake}}, a [[14 nm]] [[microarchitecture]] for enthusiasts and servers. Cascade Lake is the "Optimization" phase as part of Intel's {{intel|PAO}} model. | ||
Line 97: | Line 96: | ||
| {{intel|Cascade Lake W|l=core}} || CSL-W || || Enterprise/Business workstations | | {{intel|Cascade Lake W|l=core}} || CSL-W || || Enterprise/Business workstations | ||
|- | |- | ||
− | | {{intel|Cascade Lake SP|l=core}} || | + | | {{intel|Cascade Lake SP|l=core}} || CSL-SP || || Server Scalable Processors |
|- | |- | ||
− | | {{intel|Cascade Lake AP|l=core}} || | + | | {{intel|Cascade Lake AP|l=core}} || CSL-AP || || Server Advanced Processors |
|} | |} | ||
== Brands == | == Brands == | ||
− | Cascade Lake is sold under | + | Cascade Lake is sold under four different families. |
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | ||
Line 110: | Line 109: | ||
|- | |- | ||
! Cores !! {{intel|Hyper-Threading|HT}} !! {{intel|Turbo Boost|TBT}} !! {{x86|AVX-512}} !! AVX-512 Units !! {{intel|Ultra Path Interconnect|UPI}} links !! Scalability | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{intel|Turbo Boost|TBT}} !! {{x86|AVX-512}} !! AVX-512 Units !! {{intel|Ultra Path Interconnect|UPI}} links !! Scalability | ||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
| [[File:xeon bronze (2017).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || 6 || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}} || 1 || 2 || Up to 2 | | [[File:xeon bronze (2017).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || 6 || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}} || 1 || 2 || Up to 2 | ||
Line 125: | Line 120: | ||
| [[File:xeon platinum (2017).png|50px]] || {{intel|Xeon Platinum}} || style="text-align: left;" | Highest performance / flexibility || 4-28 || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 2 || 3 || Up to 8 | | [[File:xeon platinum (2017).png|50px]] || {{intel|Xeon Platinum}} || style="text-align: left;" | Highest performance / flexibility || 4-28 || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 2 || 3 || Up to 8 | ||
|} | |} | ||
− | |||
− | |||
=== Identification === | === Identification === | ||
Line 147: | Line 140: | ||
== Release Dates == | == Release Dates == | ||
− | Cascade Lake was released on April 2 | + | Cascade Lake was released on April 2, 2019. |
== Process Technology == | == Process Technology == | ||
Line 206: | Line 199: | ||
===== LCC SoC ===== | ===== LCC SoC ===== | ||
:[[File:skylake sp lcc block diagram.svg|500px]] | :[[File:skylake sp lcc block diagram.svg|500px]] | ||
− | |||
===== HCC SoC ===== | ===== HCC SoC ===== | ||
:[[File:skylake sp hcc block diagram.svg|600px]] | :[[File:skylake sp hcc block diagram.svg|600px]] | ||
Line 213: | Line 205: | ||
===== Individual Core ===== | ===== Individual Core ===== | ||
<small>The high-level core architecture is identical to that of {{\\|Skylake (server)#Individual Core|Skylake}}.</small> | <small>The high-level core architecture is identical to that of {{\\|Skylake (server)#Individual Core|Skylake}}.</small> | ||
− | :[[File:skylake server block diagram.svg| | + | :[[File:skylake server block diagram.svg|950px]] |
=== Memory Hierarchy === | === Memory Hierarchy === | ||
Line 253: | Line 245: | ||
*** 2,048 sets, 12-way set associative | *** 2,048 sets, 12-way set associative | ||
* DRAM | * DRAM | ||
− | ** 6 channels of DDR4, up to | + | ** 6 channels of DDR4, up to 2666 MT/s |
*** RDIMM and LRDIMM | *** RDIMM and LRDIMM | ||
− | *** bandwidth of | + | *** bandwidth of 21.33 GB/s |
− | *** aggregated bandwidth of | + | *** aggregated bandwidth of 128 GB/s |
Cascade Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). | Cascade Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). | ||
Line 359: | Line 351: | ||
One of the other features that was added in Cascade Lake is Speed Select Technology (SST) which allows a chip to be configured in the field for various workloads such as throughput and single-core performance. This is done through configurations that allow the end user to determine how the power budget is spent. For example, single-thread performance can be further increased for fewer chips by further decreasing the base frequency of more inactive core. Alternatively, higher throughput can be achieved by increasing the base frequency of some cores while reducing the base frequency of other cores. All in all, the conigurations are ultimately bound by the power budget of the chip, however the custom tweaking of frquency (base, turbo, or otherwise) enable custom tuning of affinitized workloads. | One of the other features that was added in Cascade Lake is Speed Select Technology (SST) which allows a chip to be configured in the field for various workloads such as throughput and single-core performance. This is done through configurations that allow the end user to determine how the power budget is spent. For example, single-thread performance can be further increased for fewer chips by further decreasing the base frequency of more inactive core. Alternatively, higher throughput can be achieved by increasing the base frequency of some cores while reducing the base frequency of other cores. All in all, the conigurations are ultimately bound by the power budget of the chip, however the custom tweaking of frquency (base, turbo, or otherwise) enable custom tuning of affinitized workloads. | ||
− | == | + | == Persistent Memory Support == |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | + | Intel Optane DC Persistent Memory (DCPMM) (Codename: Apache Pass) will be supported starting with Cascade Lake. The next architecture/codename is Barlow Pass. | |
− | |||
− | + | DCPMM is designed to improve overall Data Center (DC) system performance and to lower latencies by putting more data closer to the processor on NV Media. | |
− | |||
− | + | DCPMM Modules are DDR4 socket compatible, and will be available in capacities up to 512GB/Module. | |
− | |||
− | |||
− | + | === DCPMM Modules Sizes === | |
− | + | * 128GB | |
− | + | * 256GB | |
+ | * 512GB | ||
− | + | === DCPMM Specs === | |
− | + | * Capacity Per CPU: 3TB | |
− | + | * Speed 2666MT/sec | |
− | + | * Close to DRAM latency | |
+ | * Cache line size access | ||
+ | * Operational Modes | ||
+ | ** APP Direct Mode - low latency persistent memroy | ||
+ | ** Memory Mode - Used as DDR4 DRAM | ||
== Scalability == | == Scalability == |
Facts about "Cascade Lake - Microarchitectures - Intel"
codename | Cascade Lake + |
core count | 2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 +, 28 +, 32 +, 48 + and 56 + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/cascade lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cascade Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |