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== Higher core-count multi-chip processors == | == Higher core-count multi-chip processors == | ||
[[File:cascade lake ap overview.png|thumb|right|Overview slide]] | [[File:cascade lake ap overview.png|thumb|right|Overview slide]] | ||
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{{main|intel/cores/cascade_lake_ap|l1=Cascade Lake Advanced Performance}} | {{main|intel/cores/cascade_lake_ap|l1=Cascade Lake Advanced Performance}} | ||
Intel introduced a number of new products, code name {{intel|Cascade Lake Advanced Performance|l=core}}, which doubled the core count. Intel achieved this by packaging two extreme core count (XCC) dies together on the same substrate in a BGA package. The two dies are interconnected through 1 {{intel|UPI}} link which paved the way for models up to 56 cores. This was done to support a fully-connected system in a 2-way SMP system which is where those chips are designed to go. In those systems, every die is interconnected to every other die (four in total) over a {{intel|UPI}} link. With two dies per package, each CPU exposes 12 DDR4 memory channels and x40 PCIe Gen3 lanes. | Intel introduced a number of new products, code name {{intel|Cascade Lake Advanced Performance|l=core}}, which doubled the core count. Intel achieved this by packaging two extreme core count (XCC) dies together on the same substrate in a BGA package. The two dies are interconnected through 1 {{intel|UPI}} link which paved the way for models up to 56 cores. This was done to support a fully-connected system in a 2-way SMP system which is where those chips are designed to go. In those systems, every die is interconnected to every other die (four in total) over a {{intel|UPI}} link. With two dies per package, each CPU exposes 12 DDR4 memory channels and x40 PCIe Gen3 lanes. |
Facts about "Cascade Lake - Microarchitectures - Intel"
codename | Cascade Lake + |
core count | 2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 +, 28 +, 32 +, 48 + and 56 + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/cascade lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cascade Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |