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Latest revision Your text
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** Extended memory support for up to 2 TiB per socket (up from 1.5 TiB)
 
** Extended memory support for up to 2 TiB per socket (up from 1.5 TiB)
 
** Large memory support for up to 4.5 TiB per socket
 
** Large memory support for up to 4.5 TiB per socket
* I/O
 
** x64 PCIe lanes exposed to the platform (up from x48) (''{{intel|Xeon W}} only'')
 
  
 
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codenameCascade Lake +
core count2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 +, 28 +, 32 +, 48 + and 56 +
designerIntel +
first launched2019 +
full page nameintel/microarchitectures/cascade lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCascade Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +