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{{intel title|Airmont|arch}}
 
{{intel title|Airmont|arch}}
 
{{microarchitecture
 
{{microarchitecture
| atype            = CPU
 
 
| name          = Airmont
 
| name          = Airmont
 
| designer      = Intel
 
| designer      = Intel
Line 18: Line 17:
 
| speculative  = Yes
 
| speculative  = Yes
 
| renaming      = Yes
 
| renaming      = Yes
|isa=x86-64
+
| isa           = IA-32
 
+
| isa 2        = x86-64
 
| stages min    = 12
 
| stages min    = 12
 
| stages max    = 14
 
| stages max    = 14
Line 40: Line 39:
  
 
| cache        = Yes
 
| cache        = Yes
| l1i          = 32 KiB
+
| l1i          = 32 KB
 
| l1i per      = Core
 
| l1i per      = Core
 
| l1i desc      = 8-way set associative
 
| l1i desc      = 8-way set associative
| l1d          = 24 KiB
+
| l1d          = 24 KB
 
| l1d per      = Core
 
| l1d per      = Core
 
| l1d desc      = 6-way set associative
 
| l1d desc      = 6-way set associative
| l2            = 1 MiB
+
| l2            = 1 MB
 
| l2 per        = 2 Cores
 
| l2 per        = 2 Cores
 
| l2 desc      = 16-way set associative
 
| l2 desc      = 16-way set associative
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{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
! Platform !! Core !! Target
+
! Core !! Target
 +
|-
 +
| {{intel|Braswell}} || Netboooks, Tablets, Entry-level PCs
 
|-
 
|-
| {{intel|Braswell}} || {{intel|Braswell}} || Netboooks, Tablets, Entry-level PCs
+
| {{intel|Cherry Trail}} || Lightweight tablets / High-end Smartphones
 
|-
 
|-
| {{intel|Cherry Trail}} || {{intel|Cherry Trail}} || Lightweight tablets / High-end Smartphones
+
| {{intel|Riverton}} || Smartphones
|- style="text-decoration: line-through;"
 
| {{intel|Riverton}} || {{intel|Riverton}} || Smartphones (HSPA+, LTE Category 3, and TD-SCDMA)
 
|- style="text-decoration: line-through;"
 
| {{intel|Binghamton}} || {{intel|Binghamton}} || Smartphones (3G only)
 
 
|}
 
|}
  
== Process Technology ==
+
== Technology ==
{{main|intel/microarchitectures/broadwell#Process_Technology|l1=Broadwell § Process Technology}}
+
{{main|intel/microarchitectures/broadwell#technology|l1=Broadwell § Technology}}
Airmont-based chips are manufactured on Intel's [[14 nm process]].
+
Goldmont-based chips are manufactured on Intel's [[14 nm process]].
  
 
== Architecture==
 
== Architecture==
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** Hardware prefetchers
 
** Hardware prefetchers
 
** L1 Cache:
 
** L1 Cache:
*** 32 [[KiB]] 8-way [[set associative]] instruction, 64 B line size
+
*** 32 KB 8-way [[set associative]] instruction, 64 B line size
*** 24 KiB 6-way set associative data, 64 B line size
+
*** 24 KB 6-way set associative data, 64 B line size
 
*** Per core
 
*** Per core
 
** L2 Cache:
 
** L2 Cache:
*** 1 MiB 16-way set associative, 64 B line size
+
*** 1 MB 16-way set associative, 64 B line size
 
*** Per 2 cores
 
*** Per 2 cores
 
** L3 Cache:
 
** L3 Cache:
 
*** No level 3 cache
 
*** No level 3 cache
 
** RAM
 
** RAM
*** Maximum of 1 [[GiB]], 2 GiB, and 4 GiB
+
*** Maximum of 1GB, 2 GB, and 4 GB
 
*** dual 32-bit channels, 1 or 2 ranks per channel
 
*** dual 32-bit channels, 1 or 2 ranks per channel
  

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