Editing intel/microarchitectures/airmont

{{intel title|Airmont|arch}}
{{microarchitecture
| name          = Airmont
| manufacturer  = Intel
| introduction  = 2015
| phase-out     = 2017
| process       = 14 nm
| cores         = 1
| cores 2       = 2
| cores 3       = 4
| cores 4       = 8

| pipeline      = Yes
| type          = Superscalar
| OoOE          = Yes
| speculative   = Yes
| renaming      = Yes
| isa           = IA-32
| isa 2         = x86-64
| stages        = 14
| issues        = 2

| inst          = Yes
| feature       = 
| extension     = MMX
| extension 2   = SSE
| extension 3   = SSE2
| extension 4   = SSE3
| extension 5   = SSSE3
| extension 6   = SSE4
| extension 7   = SSE4.1
| extension 8   = SSE4.2
| extension 9   = VT-x
| extension 10  = AES-NI
| extension 11  = CLMUL
| extension 12  = RDRAND

| cache         = Yes
| l1i           = 32 KB
| l1i per       = Core
| l1i desc      = 8-way set associative
| l1d           = 24 KB
| l1d per       = Core
| l1d desc      = 6-way set associative
| l2            = 1 MB
| l2 per        = 2 Cores
| l2 desc       = 16-way set associative

| core names       = Yes
| core name        = Cherry Trail
| core name 2      = Braswell
| core name 3      = 
| core name 4      = 

| succession       = Yes
| predecessor      = Silvermont
| predecessor link = intel/microarchitectures/silvermont
| successor        = Goldmont
| successor link   = intel/microarchitectures/goldmont
}}
'''Airmont''' is Intel's [[14 nm]] microarchitecture for the {{intel|Atom|Atom family}} of [[system on chip]]s. Introduced in 2015, Airmont is a shrink of {{intel|Silvermont}}.

== Codenames ==
{| class="wikitable"
|-
! Platform !! Core !! Target
|-
| {{intel|Cherry Trail}} || {{intel|Cherry Trail}} || Smartphones, Tablets
|-
| {{intel|Braswell}} || {{intel|Braswell}} || Tablets, PCs
|}

== Architecture==
Airmont is for the most part identical to {{intel|Silvermont}} with some higher number of execution units to the GPU in some of the higher-end models. 

=== Key changes from {{intel|Silvermont}} ===
* DTLB table size doubled (128 entries -> 256 entries)
* L2 latency increased
* Reorder Buffer was increased (from 32 entries to 48)
* Gen 8 GPUs
=== Block Diagram ===
[[File:silvermont block.png]]

=== Memory Hierarchy ===
* Cache
** Hardware prefetchers
** L1 Cache:
*** 32 KB 8-way [[set associative]] instruction, 64 B line size
*** 24 KB 6-way set associative data, 64 B line size
*** Per core
** L2 Cache:
*** 1 MB 16-way set associative, 64 B line size
*** Per 2 cores
** L3 Cache:
*** No level 3 cache
** RAM
*** Maximum of 1GB, 2 GB, and 4 GB
*** dual 32-bit channels, 1 or 2 ranks per channel

=== Multithreading ===
Airmont, like Silvermont has no support for Intel Hyper-Threading Technology.

=== Pipeline ===
{{main|intel/microarchitectures/silvermont#Pipeline|l1=Silvermont's Pipeline}}
Airmont's pipeline is identical to {{intel|Silvermont|Silvermont's}}.

[[File:silvermont pipeline.svg]]
== Cores ==
* {{intel|Cherry Trail}} - SoCs for Smartphones/Tablets
* {{intel|Braswell}} - SoCs for low-end PCs

== All Airmont Chips ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
<table class="wikitable sortable">
<tr><th colspan="12" style="background:#D6D6FF;">Airmont Chips</th></tr>
<tr><th colspan="9">Main processor</th><th colspan="3">IGP</th></tr>
<tr><th>Model</th><th>µarch</th><th>Platform</th><th>Core</th><th>Launched</th><th>SDP</th><th>TDP</th><th>Freq</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Max Freq</th></tr>
{{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Airmont]]
 |?full page name
 |?model number
 |?microarchitecture
 |?platform
 |?core name
 |?first launched
 |?sdp
 |?tdp
 |?base frequency
 |?max memory
 |?integrated gpu
 |?integrated gpu base frequency
 |?integrated gpu max frequency
 |format=template
 |template=proc table 2
 |userparam=13
 |mainlabel=-
}}
</table>
codename	Airmont +
core count	1 +, 2 +, 4 + and 8 +
designer	Intel +
first launched	2015 +
full page name	intel/microarchitectures/airmont +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Airmont +
phase-out	2017 +
pipeline stages (max)	14 +
pipeline stages (min)	12 +
process	14 nm (0.014 μm, 1.4e-5 mm) +