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{{intel title|Airmont|arch}}
 
{{intel title|Airmont|arch}}
 
{{microarchitecture
 
{{microarchitecture
−
| atype            = CPU
 
 
| name          = Airmont
 
| name          = Airmont
−
| designer      = Intel
 
 
| manufacturer  = Intel
 
| manufacturer  = Intel
 
| introduction  = 2015
 
| introduction  = 2015
Line 18: Line 16:
 
| speculative  = Yes
 
| speculative  = Yes
 
| renaming      = Yes
 
| renaming      = Yes
−
|isa=x86-64
+
| isa           = IA-32
−
 
+
| isa 2        = x86-64
−
| stages min    = 12
+
| stages       = 14
−
| stages max    = 14
 
 
| issues        = 2
 
| issues        = 2
  
 
| inst          = Yes
 
| inst          = Yes
 
| feature      =  
 
| feature      =  
−
| extension    = MOVBE
+
| extension    = MMX
−
| extension 2  = MMX
+
| extension 2  = SSE
−
| extension 3  = SSE
+
| extension 3  = SSE2
−
| extension 4  = SSE2
+
| extension 4  = SSE3
−
| extension 5  = SSE3
+
| extension 5  = SSSE3
−
| extension 6  = SSSE3
+
| extension 6  = SSE4
 
| extension 7  = SSE4.1
 
| extension 7  = SSE4.1
 
| extension 8  = SSE4.2
 
| extension 8  = SSE4.2
−
| extension 9  = POPCNT
+
| extension 9  = VT-x
−
| extension 10  = AES
+
| extension 10  = AES-NI
−
| extension 11  = PCLMUL
+
| extension 11  = CLMUL
−
| extension 12  = RDRND
 
  
 
| cache        = Yes
 
| cache        = Yes
−
| l1i          = 32 KiB
+
| l1i          = 32 KB
 
| l1i per      = Core
 
| l1i per      = Core
 
| l1i desc      = 8-way set associative
 
| l1i desc      = 8-way set associative
−
| l1d          = 24 KiB
+
| l1d          = 24 KB
 
| l1d per      = Core
 
| l1d per      = Core
 
| l1d desc      = 6-way set associative
 
| l1d desc      = 6-way set associative
−
| l2            = 1 MiB
+
| l2            = 1 MB
 
| l2 per        = 2 Cores
 
| l2 per        = 2 Cores
 
| l2 desc      = 16-way set associative
 
| l2 desc      = 16-way set associative
Line 69: Line 65:
 
! Platform !! Core !! Target
 
! Platform !! Core !! Target
 
|-
 
|-
−
| {{intel|Braswell}} || {{intel|Braswell}} || Netboooks, Tablets, Entry-level PCs
+
| {{intel|Cherry Trail}} || {{intel|Cherry Trail}} || Smartphones, Tablets
 
|-
 
|-
−
| {{intel|Cherry Trail}} || {{intel|Cherry Trail}} || Lightweight tablets / High-end Smartphones
+
| {{intel|Braswell}} || {{intel|Braswell}} || Tablets, PCs
−
|- style="text-decoration: line-through;"
 
−
| {{intel|Riverton}} || {{intel|Riverton}} || Smartphones (HSPA+, LTE Category 3, and TD-SCDMA)
 
−
|- style="text-decoration: line-through;"
 
−
| {{intel|Binghamton}} || {{intel|Binghamton}} || Smartphones (3G only)
 
 
|}
 
|}
−
 
−
== Process Technology ==
 
−
{{main|intel/microarchitectures/broadwell#Process_Technology|l1=Broadwell § Process Technology}}
 
−
Airmont-based chips are manufactured on Intel's [[14 nm process]].
 
−
 
−
== Architecture==
 
−
Airmont is for the most part identical to {{intel|Silvermont}} with some higher number of execution units to the GPU in some of the higher-end models.
 
−
 
−
=== Key changes from {{intel|Silvermont}} ===
 
−
* DTLB table size doubled (128 entries -> 256 entries)
 
−
* L2 latency increased
 
−
* Reorder Buffer was increased (from 32 entries to 48)
 
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* Gen 8 GPUs
 
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=== Block Diagram ===
 
−
[[File:silvermont block.png]]
 
−
 
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=== Memory Hierarchy ===
 
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* Cache
 
−
** Hardware prefetchers
 
−
** L1 Cache:
 
−
*** 32 [[KiB]] 8-way [[set associative]] instruction, 64 B line size
 
−
*** 24 KiB 6-way set associative data, 64 B line size
 
−
*** Per core
 
−
** L2 Cache:
 
−
*** 1 MiB 16-way set associative, 64 B line size
 
−
*** Per 2 cores
 
−
** L3 Cache:
 
−
*** No level 3 cache
 
−
** RAM
 
−
*** Maximum of 1 [[GiB]], 2 GiB, and 4 GiB
 
−
*** dual 32-bit channels, 1 or 2 ranks per channel
 
−
 
−
=== Multithreading ===
 
−
Airmont, like Silvermont has no support for Intel Hyper-Threading Technology.
 
−
 
−
=== Pipeline ===
 
−
{{main|intel/microarchitectures/silvermont#Pipeline|l1=Silvermont's Pipeline}}
 
−
Airmont's pipeline is identical to {{intel|Silvermont|Silvermont's}}.
 
−
 
−
[[File:silvermont pipeline.svg]]
 
−
== Cores ==
 
−
* {{intel|Cherry Trail}} - SoCs for Smartphones/Tablets
 
−
* {{intel|Braswell}} - SoCs for low-end PCs
 
−
 
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== All Airmont Chips ==
 
−
<!-- NOTE:
 
−
          This table is generated automatically from the data in the actual articles.
 
−
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 
−
          created and tagged accordingly.
 
−
 
−
          Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
 
−
-->
 
−
<table class="wikitable sortable">
 
−
<tr><th colspan="12" style="background:#D6D6FF;">Airmont Chips</th></tr>
 
−
<tr><th colspan="9">Main processor</th><th colspan="3">IGP</th></tr>
 
−
<tr><th>Model</th><th>Family</th><th>Platform</th><th>Core</th><th>Launched</th><th>SDP</th><th>TDP</th><th>Freq</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Max Freq</th></tr>
 
−
{{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Airmont]]
 
−
|?full page name
 
−
|?model number
 
−
|?microprocessor family
 
−
|?platform
 
−
|?core name
 
−
|?first launched
 
−
|?sdp
 
−
|?tdp
 
−
|?base frequency
 
−
|?max memory
 
−
|?integrated gpu
 
−
|?integrated gpu base frequency
 
−
|?integrated gpu max frequency
 
−
|format=template
 
−
|template=proc table 2
 
−
|userparam=13
 
−
|mainlabel=-
 
−
}}
 
−
{{table count|col=12|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Airmont]]}}
 
−
</table>
 

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Facts about "Airmont - Microarchitectures - Intel"
RDF feed
codenameAirmont +
core count1 +, 2 +, 4 + and 8 +
designerIntel +
first launched2015 +
full page nameintel/microarchitectures/airmont +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameAirmont +
phase-out2017 +
pipeline stages (max)14 +
pipeline stages (min)12 +
process14 nm (0.014 μm, 1.4e-5 mm) +