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|chip type=neuromorphic chip
 
|chip type=neuromorphic chip
 
|name=Loihi
 
|name=Loihi
|image=loihi (front).png
+
|no image=No
|back image=loihi (back).png
 
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
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|process=14 nm
 
|process=14 nm
 
|transistors=2,070,000,000
 
|transistors=2,070,000,000
|technology=CMOS
+
|technology=FinFET
 
|die area=60 mm²
 
|die area=60 mm²
 
|max cpus=16,384
 
|max cpus=16,384
 
|v core min=0.50 V
 
|v core min=0.50 V
 
|v core max=1.25 V
 
|v core max=1.25 V
|successor=Loihi 2
 
|successor link=intel/loihi 2
 
 
|neuron count=131,072
 
|neuron count=131,072
 
|synapse count=130,000,000
 
|synapse count=130,000,000
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The chip is named after the Loihi volcano as a play-on-words - [[wikipedia:Lōʻihi Seamount|Loihi]] is an emerging Hawaiian submarine volcano that is set to surface one day.
 
The chip is named after the Loihi volcano as a play-on-words - [[wikipedia:Lōʻihi Seamount|Loihi]] is an emerging Hawaiian submarine volcano that is set to surface one day.
 
Loihi was succeeded by {{\\|Loihi 2}} in late 2021.
 
  
 
== Overview ==
 
== Overview ==
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===== Programming =====
 
===== Programming =====
 
Intel has developed a complete toolchain for working with Loihi including a Loihi Python API, a compiler, and a set of runtime libraries for building and executing SNNs on Loihi. For the most part, the API is similar to existing frameworks such as PyNN. The Loihi API provides a way of creating a graph of neurons and synapses with custom configurations such as decay time, synaptic weight, and spiking thresholds. The graphs can then be stimulated by injecting external spikes and learn through custom learning rules.
 
Intel has developed a complete toolchain for working with Loihi including a Loihi Python API, a compiler, and a set of runtime libraries for building and executing SNNs on Loihi. For the most part, the API is similar to existing frameworks such as PyNN. The Loihi API provides a way of creating a graph of neurons and synapses with custom configurations such as decay time, synaptic weight, and spiking thresholds. The graphs can then be stimulated by injecting external spikes and learn through custom learning rules.
 
== Loihi-based neuromorphic system ==
 
Intel developed a series of systems based on Loihi which scale to a large number of Neurons and Synapses.
 
 
{| class="wikitable"
 
|-
 
! Kapoho Bay !! Wolf Mountain !! Nahuku !! Pohoiki Beach !! Pohoiki Springs
 
|-
 
| USB FF || Board || FPGA Expansion Card || Multi-Board System || Many-Board System
 
|-
 
| 1-2 Chips || 4 Chips || 8 - 32 Chips || 64 Chips || 768 Chips
 
|-
 
| 130,000,000 - 260,000,000 Synapses || 520,000,000 Synapses || 1,040,000,000 - 4,160,000,000 Synapses || 8,320,000,000 Synapses || 99,840,000,000 Synapses
 
|-
 
| 131,072 - 262,144 Neurons || 524,288 Neurons || 1,048,576 - 4,194,304 Neurons || 8,388,608 Neurons || 100,663,296 Neurons
 
|}
 
 
=== Kapoho Bay (2 chip, 262K neurons) ===
 
'''Kapoho Bay''' is a USB stick form factor that incorporates 1 or 2 Loihi chips. Announced on Dec 6, 2018, Kapoho Bay includes a USB host interface and a DVS interface for neuromorphic sensors such as a camera. With 2 chip Kapoho Bay has 256 neuromorphic cores with 262,144 neurons and 260,000,000 synapses.
 
 
 
[[File:loihi kapoho bay.png|400px]]
 
 
=== Wolf Mountain (4 chip, 524K neurons) ===
 
'''Wolf Mountain''' was the first research board that shipped to researchers. This board incorporated four chips for a total of 512 neuromorphic cores meaning 524,288 neurons and 520,000,000 synapses.
 
 
 
:[[File:loihi wolf mountain.png|800px]]
 
 
=== Nahuku (32 chip, 4M neurons) ===
 
'''Nahuku''' is a scalable Arria10 FPGA expansion board. Intel uses the Nahuku board as the framework for building larger systems. The Nahuku board comes in multiple configurations from 8 to 32 chips. Those chips are organized as 16 chips in a 4 by 4 grid mesh on both sides. With 32 chips there is a total of 4,096 neuromorphic cores incorporating a total of 4,194,304 neurons and 4,160,000,000 synapses. With the Nahuku board, an FPGA host is connected to a set of conventional sensors such as actuators as well as neuromorphic sensors such as a DVS camera or a silicon cochlea. The board communicates with a standard "super host" CPU which can be used to send commands to the board and to the management core on the chips themselves.
 
 
 
:[[File:loihi nahuku board.png|800px]]
 
 
=== Pohoiki Beach (64 chip, 8M neurons)===
 
'''Pohoiki Beach''' is a scaled up system comprising two Nahuku boards for a total of 64 chips. With 64 chips there is a total of 8,192 neuromorphic cores incorporating a total of 8,388,608 neurons and 8,320,000,000 synapses.
 
 
=== Pohoiki Springs (768 chip, 100M neurons) ===
 
'''Pohoiki Springs''' is a very large scale system that consists of 24 Nahuku boards for a total of 768 Loihi chips. This system contains 8 rows with 3 slots each for 3 boards per row and eight rows for a total of 24 boards. With 24 boards in the system, there is a total of 768 chips for a total of 98,304 neuromorphic cores incorporating a total of 100,663,296 neurons and 99,840,000,000 synapses.
 
 
 
:[[File:loihi-pohoiki-springs.png|500px]]
 
  
 
== Die ==
 
== Die ==
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**  128 neuromorphic cores + 3 x86 cores
 
**  128 neuromorphic cores + 3 x86 cores
 
* 60 mm² die size
 
* 60 mm² die size
** Core area 0.41 mm²
 
  
 
* Density
 
* Density
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: [[File:intel loihi die shot.png|class=wikichip_ogimage|650px]]
 
: [[File:intel loihi die shot.png|class=wikichip_ogimage|650px]]
  
== Bibliography ==
+
== Test board ==
 +
Although Intel didn't specify, the test board appears to feature four Loihi chips meaning the board has 512 neuromorphic cores and 524,288 neurons, all are fully integrated over the mesh.
 +
 
 +
:[[File:loihi neuromorphic-test-board.png|900px]]
 +
 
 +
== References ==
 
* ''Some information was obtained directly from Intel''
 
* ''Some information was obtained directly from Intel''
 
* Jim Held, Intel Fellow & Director Emerging Technologies Research, Intel Labs, HPC Developer Conference 2017 ("Leading The Evolution of Compute: Neuromorphic and Quantum Computing").
 
* Jim Held, Intel Fellow & Director Emerging Technologies Research, Intel Labs, HPC Developer Conference 2017 ("Leading The Evolution of Compute: Neuromorphic and Quantum Computing").

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Facts about "Loihi - Intel"
back imageFile:loihi (back).png +
core voltage (max)1.25 V (12.5 dV, 125 cV, 1,250 mV) +
core voltage (min)0.5 V (5 dV, 50 cV, 500 mV) +
designerIntel +
die area60 mm² (0.093 in², 0.6 cm², 60,000,000 µm²) +
first announcedSeptember 25, 2017 +
first launchedJanuary 2018 +
full page nameintel/loihi +
instance ofneuromorphic chip +
ldateJanuary 2018 +
main imageFile:loihi (front).png +
manufacturerIntel +
market segmentArtificial Intelligence +
max cpu count16,384 +
nameLoihi +
neuron count131,072 +
process14 nm (0.014 μm, 1.4e-5 mm) +
smp max ways16,384 +
synapse count130,000,000 +
technologyCMOS +
transistor count2,070,000,000 +