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|chip type=neuromorphic chip | |chip type=neuromorphic chip | ||
|name=Loihi | |name=Loihi | ||
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|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
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|v core min=0.50 V | |v core min=0.50 V | ||
|v core max=1.25 V | |v core max=1.25 V | ||
− | + | |neuron count=130,000 | |
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|synapse count=130,000,000 | |synapse count=130,000,000 | ||
}} | }} | ||
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The chip is named after the Loihi volcano as a play-on-words - [[wikipedia:Lōʻihi Seamount|Loihi]] is an emerging Hawaiian submarine volcano that is set to surface one day. | The chip is named after the Loihi volcano as a play-on-words - [[wikipedia:Lōʻihi Seamount|Loihi]] is an emerging Hawaiian submarine volcano that is set to surface one day. | ||
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== Overview == | == Overview == | ||
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The chip consists of a [[many-core]] mesh of 128 neuromorphic cores, three {{intel|Lakemont|l=arch|Lakemont}} [[x86]] [[physical cores|cores]] ({{intel|Quark}}), and an off-chip communication interface that allows the chip to scale out to many other chips in the four planar directions (as shown on the right). The implemented mesh protocol supports up to 4,096 on-chip cores and up to 16,384 chips. | The chip consists of a [[many-core]] mesh of 128 neuromorphic cores, three {{intel|Lakemont|l=arch|Lakemont}} [[x86]] [[physical cores|cores]] ({{intel|Quark}}), and an off-chip communication interface that allows the chip to scale out to many other chips in the four planar directions (as shown on the right). The implemented mesh protocol supports up to 4,096 on-chip cores and up to 16,384 chips. | ||
− | The chip itself implements a fully asynchronous [[many-core]] [[mesh topology|mesh]] of 128 neuromorphic cores. It implements a [[spiking neural network]] (SNN) whereby at any given time one or more of the implemented neurons may send out an impulse (i.e., spike) to its neighbors through the directed links (synapses). All neurons have a local state with their own set of rules that affects their evolution and the timing of spike generation. Interaction is entirely asynchronous, sporadic, and independent of any other neuron on the network. | + | The chip itself implements a fully asynchronous [[many-core]] [[mesh topology|mesh]] of 128 neuromorphic cores. It implements a [[spiking neural network]] (SNN) whereby at any given time one or more of the implemented neurons may send out an impulse (i.e., spike) to its neighbors through the directed links (synapses). All neurons have a local state with their own set of rules that affects their evolution and the timing of spike generation. Interaction is entirely asynchronous, sporadic, and independent of any other neuron on the network. Loihi neuromorphic cores are unique due to their addition of a learning engine. The learning engine allows full on-chip learning via a programmable microcode learning rule engine. |
Core-to-core communication is done in using packetized messages with write, read request, and read response messages for core management and [[x86]]-to-x86 messaging, spike messages, and barrier messages (for synchronization). | Core-to-core communication is done in using packetized messages with write, read request, and read response messages for core management and [[x86]]-to-x86 messaging, spike messages, and barrier messages (for synchronization). | ||
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===== Programming ===== | ===== Programming ===== | ||
Intel has developed a complete toolchain for working with Loihi including a Loihi Python API, a compiler, and a set of runtime libraries for building and executing SNNs on Loihi. For the most part, the API is similar to existing frameworks such as PyNN. The Loihi API provides a way of creating a graph of neurons and synapses with custom configurations such as decay time, synaptic weight, and spiking thresholds. The graphs can then be stimulated by injecting external spikes and learn through custom learning rules. | Intel has developed a complete toolchain for working with Loihi including a Loihi Python API, a compiler, and a set of runtime libraries for building and executing SNNs on Loihi. For the most part, the API is similar to existing frameworks such as PyNN. The Loihi API provides a way of creating a graph of neurons and synapses with custom configurations such as decay time, synaptic weight, and spiking thresholds. The graphs can then be stimulated by injecting external spikes and learn through custom learning rules. | ||
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== Die == | == Die == | ||
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** 128 neuromorphic cores + 3 x86 cores | ** 128 neuromorphic cores + 3 x86 cores | ||
* 60 mm² die size | * 60 mm² die size | ||
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− | + | : [[File:intel loihi die shot.png|class=wikichip_ogimage|650px]] | |
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+ | == Test board == | ||
+ | Although Intel didn't specify, the test board appears to feature four Loihi chips meaning the board has 512 neuromorphic cores and 524,288 neurons, all are fully integrated over the mesh. | ||
− | : [[File: | + | :[[File:loihi neuromorphic-test-board.png|900px]] |
− | == | + | == References == |
* ''Some information was obtained directly from Intel'' | * ''Some information was obtained directly from Intel'' | ||
* Jim Held, Intel Fellow & Director Emerging Technologies Research, Intel Labs, HPC Developer Conference 2017 ("Leading The Evolution of Compute: Neuromorphic and Quantum Computing"). | * Jim Held, Intel Fellow & Director Emerging Technologies Research, Intel Labs, HPC Developer Conference 2017 ("Leading The Evolution of Compute: Neuromorphic and Quantum Computing"). |
Facts about "Loihi - Intel"
back image | + |
core voltage (max) | 1.25 V (12.5 dV, 125 cV, 1,250 mV) + |
core voltage (min) | 0.5 V (5 dV, 50 cV, 500 mV) + |
designer | Intel + |
die area | 60 mm² (0.093 in², 0.6 cm², 60,000,000 µm²) + |
first announced | September 25, 2017 + |
first launched | January 2018 + |
full page name | intel/loihi + |
instance of | neuromorphic chip + |
ldate | January 2018 + |
main image | + |
manufacturer | Intel + |
market segment | Artificial Intelligence + |
max cpu count | 16,384 + |
name | Loihi + |
neuron count | 131,072 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
smp max ways | 16,384 + |
synapse count | 130,000,000 + |
technology | CMOS + |
transistor count | 2,070,000,000 + |