Semiconductor & Computer Engineering
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Difference between revisions of "intel/cores/tolapai"
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| − | '''Tolapai''' is the codename for Intel's | + | '''Tolapai''' is the codename for Intel's [[system on a chip]]s based on the {{intel|Pentium M|l=arch}} microarchitecture. |
== Overview == | == Overview == | ||
Revision as of 00:07, 3 April 2017
| Edit Values | |
| Tolapai | |
 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | August 30, 2007 (announced) |
| Microarchitecture | |
| ISA | x86-32 |
| Microarchitecture | Pentium M |
| Word Size | 4 octets 32 bit8 nibbles |
| Process | 90 nm 0.09 μm 9.0e-5 mm |
| Technology | CMOS |
| Clock | 600 MHz - 1,200 MHz |
Tolapai is the codename for Intel's system on a chips based on the Pentium M microarchitecture.
Overview
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Common Features
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Members
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Documents
Facts about "Tolapai - Cores - Intel"
| designer | Intel + |
| first announced | August 30, 2007 + |
| instance of | core + |
| isa | x86-32 + |
| manufacturer | Intel + |
| microarchitecture | Pentium M + |
| name | Tolapai + |
| process | 90 nm (0.09 μm, 9.0e-5 mm) + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + |