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Information for "intel/cores/cascade lake sp"

Basic information

Display titleCascade Lake SP - Cores - Intel
Default sort keyCascade Lake SP, Intel
Page length (in bytes)9,614
Page ID29228
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page4
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

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Edit history

Page creatorDavid (talk | contribs)
Date of page creation20:13, 7 April 2018
Latest editorDavid (talk | contribs)
Date of latest edit12:48, 27 February 2020
Total number of edits30
Total number of distinct authors2
Recent number of edits (within past 90 days)0
Recent number of distinct authors0

Page properties

Transcluded templates (20)

Templates used on this page:

chipsetLewisburg +
designerIntel +
first announcedMay 16, 2017 +
first launchedDecember 2018 +
instance ofcore +
isax86-64 +
main imageFile:skylake sp (basic).png + and File:skylake-sp (hfi).png +
main image captionCascade Lake SP, with HFI +
manufacturerIntel +
microarchitectureCascade Lake +
nameCascade Lake SP +
packageFCLGA-3647 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
socketSocket P + and LGA-3647 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +