From WikiChip
Information for "intel/cores/cascade lake r"

Basic information

Display titleCascade Lake R - Cores - Intel
Default sort keyCascade Lake R, Intel
Page length (in bytes)8,017
Page ID35930
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page1
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

Page protection

EditAllow all users (infinite)
MoveAllow all users (infinite)

Edit history

Page creatorDavid (talk | contribs)
Date of page creation13:35, 27 February 2020
Latest editorDavid (talk | contribs)
Date of latest edit11:25, 28 February 2020
Total number of edits6
Total number of distinct authors1
Recent number of edits (within past 90 days)0
Recent number of distinct authors0

Page properties

Transcluded templates (20)

Templates used on this page:

chipsetLewisburg +
designerIntel +
first announcedFebruary 24, 2020 +
first launchedFebruary 24, 2020 +
instance ofcore +
isax86-64 +
isa familyx86 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
microarchitectureCascade Lake +
nameCascade Lake R +
packageFCLGA-3647 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
socketSocket P + and LGA-3647 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +