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Atom Z540 - Intel
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Template:mpu Z540 is an ultra-low power 32-bit x86 microprocessor introduced by Intel in early 2008 specifically for Mobile Internet Devices (MID). The Z540, which is based on the Bonnell microarchitecture (Silverthorne core), is manufactured on a 45 nm process. This processor operates at 1.86 Ghz with a TDP of 2.4 W and an average power of 220 mW. The MPU features a legacy 533 MT/s front-side bus capable of communicating with the Poulsbo chipset in both low-power CMOS mode as well as normal GTL mode (which also works with other chipsets).

This processor has a TDP of 2.4 W when Hyper-Threading is disabled and 2.64 W when enabled.

Cache

Main article: Bonnell § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$56 KiB
57,344 B
0.0547 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$24 KiB
24,576 B
0.0234 MiB
1x24 KiB6-way set associativewrite-back

L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB8-way set associative 

Memory controller

This processor has no integrated memory controller.

Graphics

This processor has no integrated graphics.

Features

Die Shot

See also: Bonnell § Silverthorne Die
  • 45 nm process
  • 9 metal layers
  • 47,212,207 transistors
  • 3.1 mm x 7.8 mm
  • 24.18 mm² die size

Silverthorne die shot.jpg


Silverthorne die shot (marked).png

Facts about "Atom Z540 - Intel"
has featureHyper-Threading Technology + and Enhanced SpeedStep Technology +
has intel enhanced speedstep technologytrue +
has simultaneous multithreadingtrue +
l1$ size56 KiB (57,344 B, 0.0547 MiB) +
l1d$ description6-way set associative +
l1d$ size24 KiB (24,576 B, 0.0234 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +