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'''Atom 330''' is an ultra-low power {{arch|64}} [[x86]] [[dual-core]] microprocessor introduced by [[Intel]] in late 2008. The 330 is specifically designed for nettops and various other mobile internet connected devices. This processors, which was fabricated on Intel's [[45 nm process]], was based on the {{intel|Bonnell|l=arch}} microarchitecture. The Atom 330 operates at 1.6 GHz with a TDP of 8 W with an average power consumption of 1.2 W. The MPU features a legacy [[QDR]] 533 MT/s [[front-side bus]].
 
'''Atom 330''' is an ultra-low power {{arch|64}} [[x86]] [[dual-core]] microprocessor introduced by [[Intel]] in late 2008. The 330 is specifically designed for nettops and various other mobile internet connected devices. This processors, which was fabricated on Intel's [[45 nm process]], was based on the {{intel|Bonnell|l=arch}} microarchitecture. The Atom 330 operates at 1.6 GHz with a TDP of 8 W with an average power consumption of 1.2 W. The MPU features a legacy [[QDR]] 533 MT/s [[front-side bus]].
  
−
The Atom 330 is actually two identical {{\\|230|Atom 230}} dies packaged together to form a dual-core Atom processor; it thus has exactly twice as many transistors, occupy twice the die size, and consume twice as much power as the {{\\|230}}.
+
The Atom 330 is actually two identical {{\\|230|Atom 230}} dies packaged together to form a dual-core Atom processor; it thus has exactly twice as many transistors, occupy twice the die size, and consumes twice as much power as the {{\\|230}}.
 +
 
 +
== Cache ==
 +
{{main|intel/microarchitectures/bonnell#Memory_Hierarchy|l1=Bonnell § Cache}}
 +
{{cache size
 +
|l1 cache=112 KiB
 +
|l1i cache=64 KiB
 +
|l1i break=2x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=48 KiB
 +
|l1d break=2x24 KiB
 +
|l1d desc=6-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=1 MiB
 +
|l2 break=2x512 KiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 
 +
== Memory controller ==
 +
This processor has no integrated memory controller.
 +
 
 +
== Graphics ==
 +
This processor has no integrated graphics.
 +
 
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=No
 +
|sse42=No
 +
|sse4a=No
 +
|avx=No
 +
|avx2=No
 +
|avx512=No
 +
|abm=No
 +
|tbm=No
 +
|bmi1=No
 +
|bmi2=No
 +
|fma3=No
 +
|fma4=No
 +
|aes=No
 +
|rdrand=No
 +
|sha=No
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=No
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=Yes
 +
|vpro=No
 +
|vtx=No
 +
|vtd=No
 +
|ept=No
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}
 +
 
 +
== Documents ==
 +
=== Datasheets ===
 +
* [[:File:atom-330-datasheet.pdf|Atom 330 Datasheet]], April 2010
 +
=== Other ===
 +
* [[:File:atom-300-specification-update.pdf|Atom 300 Series Specification Update]], April 2010
 +
* [[:File:atom-300-guide.pdf|Atom 300 Series Thermal and Mechanical Design Guidelines]], September 2008

Revision as of 20:19, 15 April 2017

Template:mpu Atom 330 is an ultra-low power 64-bit x86 dual-core microprocessor introduced by Intel in late 2008. The 330 is specifically designed for nettops and various other mobile internet connected devices. This processors, which was fabricated on Intel's 45 nm process, was based on the Bonnell microarchitecture. The Atom 330 operates at 1.6 GHz with a TDP of 8 W with an average power consumption of 1.2 W. The MPU features a legacy QDR 533 MT/s front-side bus.

The Atom 330 is actually two identical Atom 230 dies packaged together to form a dual-core Atom processor; it thus has exactly twice as many transistors, occupy twice the die size, and consumes twice as much power as the 230.

Cache

Main article: Bonnell § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$112 KiB
114,688 B
0.109 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$48 KiB
49,152 B
0.0469 MiB
2x24 KiB6-way set associativewrite-back
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  2x512 KiB8-way set associative 

Memory controller

This processor has no integrated memory controller.

Graphics

This processor has no integrated graphics.

Features

Documents

Datasheets

Other

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Facts about "Atom 330 - Intel"
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has featureHyper-Threading Technology +
has simultaneous multithreadingtrue +
l1$ size112 KiB (114,688 B, 0.109 MiB) +
l1d$ description6-way set associative +
l1d$ size48 KiB (49,152 B, 0.0469 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +