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|predecessor=z13 | |predecessor=z13 | ||
|predecessor link=ibm/microarchitectures/z13 | |predecessor link=ibm/microarchitectures/z13 | ||
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}} | }} | ||
− | '''z14''' | + | '''z14''' was a [[z/Architecture]]-based microarchitecture designed by [[IBM]] and introduced in 2017 for their {{ibm|z14}} processors and mainframes. The z14 microarchitecture replaced the {{\\|z13}}. |
==Process Technology== | ==Process Technology== | ||
− | z14-based microprocessors are manufactured on [[GlobalFoundries]]'s [[14 nm process|14 nm]] (14HP) [[FinFET]] [[Silicon-On-Insulator]] (SOI) process | + | z14-based microprocessors are manufactured on [[GlobalFoundries]]'s [[14 nm process|14 nm]] (14HP) [[FinFET]] [[Silicon-On-Insulator]] (SOI) process. The process was designed by IBM at what used to be their East Fishkill, New York fab which has since been sold to GlobalFoundries. |
== Release Dates == | == Release Dates == | ||
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** New support for [[SHA-3]] standard | ** New support for [[SHA-3]] standard | ||
− | {{expand | + | {{expand section}} |
==== New instructions ==== | ==== New instructions ==== | ||
* New [[SIMD]] instructions for [[COBOL]] and analytics applications | * New [[SIMD]] instructions for [[COBOL]] and analytics applications | ||
== Overview == | == Overview == | ||
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== Die == | == Die == | ||
− | + | === Core === | |
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Below is a layout of a single [[physical core]]: | Below is a layout of a single [[physical core]]: | ||
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* '''IDU''' - Instruction decode unit | * '''IDU''' - Instruction decode unit | ||
* '''IFB''' - Instruction fetch and branch prediction | * '''IFB''' - Instruction fetch and branch prediction | ||
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+ | === Single-chip module (SCM) === | ||
+ | IBM's z14 Single-Chip Module (SCM) consists of a multi-layer metal substrate module that includes either: | ||
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+ | * 1x Processor Unit (PU) | ||
+ | * 1x System Controller (SC) | ||
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+ | === Processor Unit (PU) Chip === | ||
+ | * [[IBM]]'s developed (now GlobalFoundries) [[14 nm process|14HP Process]] | ||
+ | ** CMOS FinFET SOI | ||
+ | ** 17 Metal Layers | ||
+ | * [[deca-core]] | ||
+ | * 5.2 GHz (192 ps cycle time) | ||
+ | * 6,100,000,000 transistors | ||
+ | * 14.4 miles of copper wire | ||
+ | * 26.5 x 27.8 mm die | ||
+ | ** 736.7 mm² die size | ||
+ | ** 18,581 power pins | ||
+ | ** 1,505 signal pins | ||
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+ | :: [[File:z14 die floor plan.png|650px]] | ||
=== System Controller (SC) Chip === | === System Controller (SC) Chip === | ||
− | [[ | + | * [[IBM]]'s developed (now GlobalFoundries) [[14 nm process|14HP Process]] |
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** CMOS FinFET SOI | ** CMOS FinFET SOI | ||
** 17 Metal Layers | ** 17 Metal Layers | ||
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:: [[File:ibm z14 sc floor plan.png|650px]] | :: [[File:ibm z14 sc floor plan.png|650px]] | ||
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Facts about "z14 - Microarchitectures - IBM"
codename | z14 + |
core count | 7 +, 8 +, 9 + and 10 + |
designer | IBM + |
first launched | July 17, 2017 + |
full page name | ibm/microarchitectures/z14 + |
instance of | microarchitecture + |
instruction set architecture | z/Architecture + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | z14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |