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== Architecture ==
 
== Architecture ==
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[[File:hi1620 overview.png|500px|thumb|right|Overview]]
 
 
=== Key changes from {{\\|TaiShan v100}} ===
 
=== Key changes from {{\\|TaiShan v100}} ===
 
* [[TSMC]] [[7 nm|7 nm HPC process]] (from [[16 nm]])
 
* [[TSMC]] [[7 nm|7 nm HPC process]] (from [[16 nm]])
 
* 2x [[core count]] (64, up from 32)
 
* 2x [[core count]] (64, up from 32)
 
** Custom cores (from {{armh|Cortex-A72|l=arch}})
 
** Custom cores (from {{armh|Cortex-A72|l=arch}})
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*** ASIMD
 
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**** double SP Vector throughput (2 inst/cycle, up from 1)
 
 
* Memory
 
* Memory
 
** 2x memory channels (8, up from 4)
 
** 2x memory channels (8, up from 4)
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** L1I Cache
 
** L1I Cache
 
*** 64 KiB/core, private
 
*** 64 KiB/core, private
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*** 64-byte cache lines
 
 
** L1D Cache
 
** L1D Cache
 
*** 64 KiB/core, private
 
*** 64 KiB/core, private
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*** 64-byte cache lines
 
 
** L2 Cache
 
** L2 Cache
 
*** 512 KiB/core, private
 
*** 512 KiB/core, private
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== Overview ==
 
== Overview ==
 
[[File:taishan v110 overview.svg|right|500px|thumb|Overview]]
 
[[File:taishan v110 overview.svg|right|500px|thumb|Overview]]
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Though HiSilicon has a history of designing Arm processors. The TaiShan v110 core is HiSilicons' first custom homegrown high-performance [[ARM]] core and SoC design. The chip, which incorporates multiple compute dies and an I/O is a multi-chip package, is fabricated on [[TSMC]]'s [[7 nm|7-nanometers HPC process]] and integrates up to 64 cores and up to 64 MiB of [[last level cache]].
+
Though HiSilicon has a history of designing Arm processors. The TaiShan v110 core is HiSilicons' first custom homegrown high-performance [[ARM]] core and SoC design. The chip, which incorporates multiple compute dies and an I/O is a multi-chip package, is fabricated on [[TSMC]]'s [[7 nm process]] and integrates up to 64 cores and up to 64 MiB of [[last level cache]].
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The SoC also incorporates a number of [[hardware accelerators]]. There is a crypto engine that supports AES, DES/3DES, MD5, SHA1, SHA2, HMAC, CMAC with throughputs of up to 100 Gbit/s. Additionally, there is also a compression engine supporting GZIP, LZS, LZ4 with compression throughputs of up to 40 Gbit/s and decompression of up to 100 Gbit/s.
 
  
 
Marketed as the Kunpeng 920, this SoC supports up to 4-way multiprocessing support through HiSilicon's Hydra interface. In order to keep the cores fed, eight [[DDR4]] [[memory channels]] are incorporated per socket. Additionally, designed to facilitate an easy [[accelerator]] platform, there are 40 PCIe Gen 4 lanes provided per socket with [[CCIX]] support, enabling cache coherency.
 
Marketed as the Kunpeng 920, this SoC supports up to 4-way multiprocessing support through HiSilicon's Hydra interface. In order to keep the cores fed, eight [[DDR4]] [[memory channels]] are incorporated per socket. Additionally, designed to facilitate an easy [[accelerator]] platform, there are 40 PCIe Gen 4 lanes provided per socket with [[CCIX]] support, enabling cache coherency.
  
 
== Core ==
 
== Core ==
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Each core is a 4-way out-of-order superscalar that implements the [[ARMv8.2]]-A ISA. Huawei stated that the core supports almost all the [[ARMv8.4]] features with a few exceptions, including dot product and the FP16 FML extension. It features private 64 KiB L1 instruction and data caches as well as 512 KiB of private L2. Though light on details, Huawei says that compared to Arm's {{armh|Cortex}} cores, their core features an improved memory subsystem, a larger number of execution units, and a better branch predictor.
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{{empty section}}
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=== ASIMD ===
 
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Each core features a single 128-bit {{arm|NEON}} unit. It is capable of executing single double-precision FMA vector instruction per cycle or two single-precision vector instructions per cycle. Operating at 2 GHz, a 64-core chip will have a peak compute of 512 GigaFLOPS of [[double-precision floating point]]. It's worth noting that compared to the {{\\|TaiShan v100}}, the throughput for single-precision vector has been doubled from 1 to 2 instructions per cycle.
 
  
 
== MCP physical design ==
 
== MCP physical design ==
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:[[File:Kunpeng 920 4smp.svg|600px]]
 
:[[File:Kunpeng 920 4smp.svg|600px]]
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== Chipset ==
 
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Along with the Hi1620 SoC, HiSilicon developed a number of integrated circuits as part of the chipset platform.
 
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{| class="wikitable"
 
−
|-
 
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! Chip !! Description
 
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|-
 
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| Hi1620 || CPU, Kunpeng 920 series Chip
 
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|-
 
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| Hi1503 || CPU interconnect chip, supports scaling-up to 32 sockets
 
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|-
 
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| Hi1812 || SSD  storage controller, for read/write I/O acceleration
 
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|-
 
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| Hi1822 || Network controller chip, DC high-speed flexible interconnect
 
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|-
 
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| Hi1710 || BMC management chip + enhanced RAS features chip
 
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|}
 
−
 
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:[[File:hi1620 chipset.png|600px]]
 
  
 
== Die ==
 
== Die ==
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** 3-4 dies
 
** 3-4 dies
  
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== All TaiShan v110 Chips ==
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== All TaiShan Chips ==
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{{comp table start}}
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{{empty section}}
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<table class="comptable sortable tc4">
 
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{{comp table header|main|6:List of TaiShan v110-based Processors}}
 
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{{comp table header|cols|Launched|Cores|Arch|%Frequency|L3|TDP}}
 
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{{#ask: [[Category:microprocessor models by hisilicon]] [[core name::TaiShan v110]]
 
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|?full page name
 
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|?model number
 
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|?first launched
 
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|?core count
 
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|?core name
 
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|?base frequency#GHz
 
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|?l3$ size
 
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|?tdp
 
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|format=template
 
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|template=proc table 3
 
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|userparam=8
 
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|mainlabel=-
 
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}}
 
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{{comp table count|ask=[[Category:microprocessor models by hisilicon]] [[core name::TaiShan v110]]}}
 
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</table>
 
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{{comp table end}}
 
  
 
== Bibliography ==
 
== Bibliography ==
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* Huawei Connect 2018. October 2018
 
* Huawei Connect 2018. October 2018
 
* HiSilicon Event. January 7, 2019
 
* HiSilicon Event. January 7, 2019
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* Huawei, Supercomputing 2018
 

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Facts about "TaiShan v110 - Microarchitectures - HiSilicon"
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codenameTaiShan v110 +
core count32 +, 48 + and 64 +
designerHiSilicon +
first launched2019 +
full page namehisilicon/microarchitectures/taishan v110 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2-A +
manufacturerTSMC +
microarchitecture typeCPU +
nameTaiShan v110 +
process7 nm (0.007 μm, 7.0e-6 mm) +