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Difference between revisions of "hisilicon/kunpeng/hi1610"
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|model number=Hi1610 | |model number=Hi1610 | ||
|market=Server | |market=Server | ||
+ | |first announced=2015 | ||
+ | |first launched=2015 | ||
|family=Hi16xx | |family=Hi16xx | ||
+ | |frequency=2,100 MHz | ||
|isa=ARMv8 | |isa=ARMv8 | ||
|isa family=ARM | |isa family=ARM | ||
+ | |microarch=Cortex-A57 | ||
+ | |core name=Cortex-A57 | ||
+ | |process=16 nm | ||
+ | |technology=CMOS | ||
+ | |word size=64 bit | ||
+ | |core count=16 | ||
+ | |thread count=16 | ||
+ | |max cpus=2 | ||
+ | |max memory=128 GiB | ||
}} | }} | ||
+ | '''Hi1610''' is a [[hexadeca-core]] {{arch|64}} [[ARM]] server microprocessor introduced by HiSilicon in late 2015. Fabricated by [[TSMC]] on a [[16 nm process]], this chip incorporates 16 {{armh|Cortex-A57}} cores operating at 2.1 GHz. The Hi1610 supports up to 128 GiB of dual-channel DDR4-1866 memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A57 § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=1.25 MiB | ||
+ | |l1i cache=768 KiB | ||
+ | |l1i break=16x48 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=512 KiB | ||
+ | |l1d break=16x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l2 cache=4 MiB | ||
+ | |l2 break=16x256 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l3 cache=16 MiB | ||
+ | |l3 break=16x1 MiB | ||
+ | |l3 desc=16-way set associative | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-1866 | ||
+ | |ecc=Yes | ||
+ | |max mem=256 GiB | ||
+ | |controllers=1 | ||
+ | |channels=2 | ||
+ | |width=64 bit | ||
+ | |max bandwidth=55.63 GiB/s | ||
+ | |bandwidth schan=13.91 GiB/s | ||
+ | |bandwidth dchan=27.81 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=16 | ||
+ | |pcie config=2x8 | ||
+ | }} | ||
+ | }} | ||
+ | == Features == | ||
+ | {{arm features | ||
+ | |thumb=No | ||
+ | |thumb2=No | ||
+ | |thumbee=No | ||
+ | |vfpv1=No | ||
+ | |vfpv2=No | ||
+ | |vfpv3=No | ||
+ | |vfpv3-d16=No | ||
+ | |vfpv3-f16=No | ||
+ | |vfpv4=No | ||
+ | |vfpv4-d16=No | ||
+ | |vfpv5=No | ||
+ | |neon=Yes | ||
+ | |trustzone=No | ||
+ | |jazelle=No | ||
+ | |wmmx=No | ||
+ | |wmmx2=No | ||
+ | |pmuv3=No | ||
+ | |crc32=Yes | ||
+ | |crypto=No | ||
+ | |fp=No | ||
+ | |fp16=No | ||
+ | |profile=No | ||
+ | |ras=No | ||
+ | |simd=No | ||
+ | |rdm=No | ||
+ | }} | ||
+ | == Utilizing devices == | ||
+ | * [[used by::HiSilicon D02]] | ||
+ | |||
+ | {{expand list}} |
Latest revision as of 03:03, 17 July 2019
Edit Values | |
Hi1610 | |
General Info | |
Designer | HiSilicon, ARM Holdings |
Manufacturer | TSMC |
Model Number | Hi1610 |
Market | Server |
Introduction | 2015 (announced) 2015 (launched) |
General Specs | |
Family | Hi16xx |
Frequency | 2,100 MHz |
Microarchitecture | |
ISA | ARMv8 (ARM) |
Microarchitecture | Cortex-A57 |
Core Name | Cortex-A57 |
Process | 16 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 16 |
Threads | 16 |
Max Memory | 128 GiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Hi1610 is a hexadeca-core 64-bit ARM server microprocessor introduced by HiSilicon in late 2015. Fabricated by TSMC on a 16 nm process, this chip incorporates 16 Cortex-A57 cores operating at 2.1 GHz. The Hi1610 supports up to 128 GiB of dual-channel DDR4-1866 memory.
Cache[edit]
- Main article: Cortex-A57 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
Supported ARM Extensions & Processor Features
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Utilizing devices[edit]
- HiSilicon D02
This list is incomplete; you can help by expanding it.
Facts about "Hi1610 - HiSilicon"
designer | HiSilicon + and ARM Holdings + |
family | Hi16xx + |
full page name | hisilicon/kunpeng/hi1610 + |
instance of | microprocessor + |
isa | ARMv8 + |
isa family | ARM + |
ldate | 1900 + |
manufacturer | TSMC + |
market segment | Server + |
model number | Hi1610 + |
name | Hi1610 + |