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{{graphcore title|Colossus|l=arch}}
 
{{graphcore title|Colossus|l=arch}}
{{microarchitecture
+
{{microarchitecture}}
|atype=NPU
 
|name=Colossus
 
|designer=Graphcore
 
|manufacturer=TSMC
 
|introduction=2018
 
|process=16 nm
 
}}
 
 
'''Colossus''' is a [[16 nm]] microarchitecture for high-performance [[neural processors]] designed by [[Graphcore]] set to be introduced in late-2018.
 
'''Colossus''' is a [[16 nm]] microarchitecture for high-performance [[neural processors]] designed by [[Graphcore]] set to be introduced in late-2018.
  
 
== Etymology ==
 
== Etymology ==
 
Codename Colossus was chosen in honor of [[Tommy Flowers]] and the [[Colossus]] computer.
 
Codename Colossus was chosen in honor of [[Tommy Flowers]] and the [[Colossus]] computer.
 
== Process Technology ==
 
Colossus is designed to be fabricated on [[TSMC]]'s [[16 nm FinFET process]].
 
 
== Architecture ==
 
{{empty section}}
 
 
== Die ==
 
=== Floorplan ===
 
* [[16 nm process]]
 
* ~800 mm² die size
 
* 23,647,173,309 transistors
 
* 1,216 PUs
 
** 2 Grids of 608 PUs each
 
*** 8 x 19 blocks
 
**** 4 PUs / block
 
** 300 MiB on-die memory
 
 
 
:[[File:colossus floorplan.png|500px]]
 
 
 
:[[File:colossus floorplan (annotated).png|500px]]
 

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Facts about "Colossus - Graphcore"
codenameColossus +
designerGraphcore +
first launched2018 +
full page namegraphcore/microarchitectures/colossus +
instance ofmicroarchitecture +
manufacturerTSMC +
nameColossus +
process16 nm (0.016 μm, 1.6e-5 mm) +