Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "esperanto/microarchitectures/et-minion"
| Line 8: | Line 8: | ||
|process=7 nm | |process=7 nm | ||
|type=Superscalar | |type=Superscalar | ||
| − | |type 2= | + | |type 2=Pipelined |
| − | |oooe= | + | |oooe=No |
|speculative=Yes | |speculative=Yes | ||
| − | |renaming= | + | |renaming=No |
|isa=RV64 | |isa=RV64 | ||
|extension=I | |extension=I | ||
| Line 19: | Line 19: | ||
|extension 5=D | |extension 5=D | ||
|extension 6=C | |extension 6=C | ||
| − | |||
| − | |||
|contemporary=ET-Maxion | |contemporary=ET-Maxion | ||
|contemporary link=esperanto/microarchitectures/et-maxion | |contemporary link=esperanto/microarchitectures/et-maxion | ||
}} | }} | ||
Revision as of 21:23, 25 December 2017
| Edit Values | |
| ET-Minion µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Esperanto |
| Manufacturer | TSMC |
| Introduction | 2018 |
| Process | 7 nm |
| Pipeline | |
| Type | Superscalar, Pipelined |
| OoOE | No |
| Speculative | Yes |
| Reg Renaming | No |
| Instructions | |
| ISA | RV64 |
| Extensions | I, M, A, F, D, C |
| Contemporary | |
| ET-Maxion | |
Facts about "ET-Minion - Microarchitectures - Esperanto"
| codename | ET-Minion + |
| designer | Esperanto + |
| first launched | 2018 + |
| full page name | esperanto/microarchitectures/et-minion + |
| instance of | microarchitecture + |
| instruction set architecture | RV64 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | ET-Minion + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |
