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}} | }} | ||
{{dec proc tech |year=1986 |name=CMOS-1 |mlayers=2 |node=2 µm | {{dec proc tech |year=1986 |name=CMOS-1 |mlayers=2 |node=2 µm | ||
| − | |archs= | + | |archs=CVAX |
| − | |a1=T<sub>ox</sub> |d1= | + | |a1=T<sub>ox</sub> |d1=30 nm |a12=Masks |d12=12 |
| − | |a2=L<sub>g</sub> | | + | |a2=V<sub>dd</sub> |d2=5 V |
| + | |a3=L<sub>g</sub> |d3=2 µm | ||
}} | }} | ||
{{dec proc tech |year=1988 |name=CMOS-2 |mlayers=2 |node=1.5 µm | {{dec proc tech |year=1988 |name=CMOS-2 |mlayers=2 |node=1.5 µm | ||
| − | |archs= | + | |archs=CVAX+, Rigel |
| − | |a1=T<sub>ox</sub> |d1= | + | |a1=T<sub>ox</sub> |d1=22.5 nm |a12=Masks |d12=13 |
| − | |a2=L<sub>g</sub> | | + | |a2=V<sub>dd</sub> |d2=5 V |
| + | |a3=L<sub>g</sub> |d3=1.5 µm | ||
}} | }} | ||
{{dec proc tech |year=1990 |name=CMOS-3 |mlayers=2 |node=1 µm | {{dec proc tech |year=1990 |name=CMOS-3 |mlayers=2 |node=1 µm | ||
| − | |archs= | + | |archs=Mariah |
| − | |a1=T<sub>ox</sub> |d1= | + | |a1=T<sub>ox</sub> |d1=15 nm |a12=Masks |d12=20 |
| − | |a2=L<sub>g</sub> | | + | |a2=V<sub>dd</sub> |d2=3.3 V |
| + | |a3=L<sub>g</sub> |d3=1 µm | ||
}} | }} | ||
{{dec proc tech |year=1991 |name=CMOS-4 |mlayers=3 |node=0.75 µm | {{dec proc tech |year=1991 |name=CMOS-4 |mlayers=3 |node=0.75 µm | ||
|archs=NVAX, Alpha 21064 | |archs=NVAX, Alpha 21064 | ||
| − | |a1=T<sub>ox</sub> |d1=10.5 nm | + | |a1=T<sub>ox</sub> |d1=10.5 nm |a12=Masks |d12=21 |
|a2=V<sub>dd</sub> |d2=3.3 V |a22=SRAM |d22= 100 µm² | |a2=V<sub>dd</sub> |d2=3.3 V |a22=SRAM |d22= 100 µm² | ||
|a3=L<sub>g</sub> |d3=0.75 µm |a32=L<sub>eff</sub> |d32=0.50 µm | |a3=L<sub>g</sub> |d3=0.75 µm |a32=L<sub>eff</sub> |d32=0.50 µm | ||
}} | }} | ||
{{dec proc tech |year=1996 |name=CMOS-4S |mlayers=3 |node=0.675 µm | {{dec proc tech |year=1996 |name=CMOS-4S |mlayers=3 |node=0.675 µm | ||
| − | |archs=NVAX, NVAX+ | + | |archs=NVAX, NVAX+, SOC |
|a1=T<sub>ox</sub> |d1= | |a1=T<sub>ox</sub> |d1= | ||
| + | |a2=L<sub>g</sub> |d2=0.675 µm | ||
}} | }} | ||
| − | {{dec proc tech |year=1994 |name=CMOS-5 |mlayers=4 |node=0. | + | {{dec proc tech |year=1994 |name=CMOS-5 |mlayers=4 |node=0.50 µm |
|archs=NVAX++ | |archs=NVAX++ | ||
|a1=T<sub>ox</sub> |d1= | |a1=T<sub>ox</sub> |d1= | ||
| + | |a2=L<sub>g</sub> |d2=0.50 µm | ||
}} | }} | ||
{{dec proc tech |year=1996 |name=CMOS-6 |mlayers=4 |node=0.35 µm | {{dec proc tech |year=1996 |name=CMOS-6 |mlayers=4 |node=0.35 µm | ||
|archs= | |archs= | ||
| − | |a1=T<sub>ox</sub> |d1= | + | |a1=T<sub>ox</sub> |d1=6 nm |
| + | |a2=L<sub>g</sub> |d2=0.35 µm |a22=L<sub>eff</sub> |d22=0.25 µm | ||
}} | }} | ||
{{dec proc tech |year=1997 |name=CMOS-7 |mlayers=5 |node=0.25 µm | {{dec proc tech |year=1997 |name=CMOS-7 |mlayers=5 |node=0.25 µm | ||
| Line 54: | Line 60: | ||
</table> | </table> | ||
</div> | </div> | ||
| + | |||
| + | Additionally, DEC fabricated on Motorola's [[ECL]] process: | ||
| + | |||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | | Mosaic1 || 3 µm ECL | ||
| + | |- | ||
| + | | Mosaic2 || 1 µm ECL | ||
| + | |- | ||
| + | | Mosaic3 || | ||
| + | |} | ||
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Revision as of 18:49, 11 June 2017
This article details details DEC's Semiconductor Process Technology history for research and posterity.
The table below shows the history of DEC's process scaling. Values were taken from various DEC documents including historical presentations and journals, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between DEC's own documents and therefore discrepancies may exist.
Timeline
| Year | Process | Node | MLayers | µarchs | Attributes | |||
|---|---|---|---|---|---|---|---|---|
| 1984 | ZMOS | 3 µm | 2 | V-11, MicroVAX II | Tox | 43 nm | ||
| Lg | 3 µm | |||||||
| 1986 | CMOS-1 | 2 µm | 2 | CVAX | Tox | 30 nm | Masks | 12 |
| Vdd | 5 V | |||||||
| Lg | 2 µm | |||||||
| 1988 | CMOS-2 | 1.5 µm | 2 | CVAX+, Rigel | Tox | 22.5 nm | Masks | 13 |
| Vdd | 5 V | |||||||
| Lg | 1.5 µm | |||||||
| 1990 | CMOS-3 | 1 µm | 2 | Mariah | Tox | 15 nm | Masks | 20 |
| Vdd | 3.3 V | |||||||
| Lg | 1 µm | |||||||
| 1991 | CMOS-4 | 0.75 µm | 3 | NVAX, Alpha 21064 | Tox | 10.5 nm | Masks | 21 |
| Vdd | 3.3 V | SRAM | 100 µm² | |||||
| Lg | 0.75 µm | Leff | 0.50 µm | |||||
| 1996 | CMOS-4S | 0.675 µm | 3 | NVAX, NVAX+, SOC | Tox | |||
| Lg | 0.675 µm | |||||||
| 1994 | CMOS-5 | 0.50 µm | 4 | NVAX++ | Tox | |||
| Lg | 0.50 µm | |||||||
| 1996 | CMOS-6 | 0.35 µm | 4 | Tox | 6 nm | |||
| Lg | 0.35 µm | Leff | 0.25 µm | |||||
| 1997 | CMOS-7 | 0.25 µm | 5 | Tox | ||||
| 1997 | Fab-6 in Hudson, Mass was sold to Intel which consequently upgraded it for $800M to Intel's propiatery 0.18 µm (see Intel's Process). | |||||||
| 2013 | In late 2013 Intel announced that it will be closing the Hudson Fab due to no longer meeting their requirements such as aging technology. | |||||||
Additionally, DEC fabricated on Motorola's ECL process:
| Mosaic1 | 3 µm ECL |
| Mosaic2 | 1 µm ECL |
| Mosaic3 |
