Semiconductor & Computer Engineering
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Difference between revisions of "chip multiprocessor"
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== Multi-core chips == | == Multi-core chips == | ||
{{collist | {{collist | ||
| − | | count = | + | | count = 4 |
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* {{\\|2|2 (dual-core)}} | * {{\\|2|2 (dual-core)}} | ||
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* {{\\|48|48 (octatetraconta-core)}} | * {{\\|48|48 (octatetraconta-core)}} | ||
* {{\\|64|64 (tetrahexaconta-core)}} | * {{\\|64|64 (tetrahexaconta-core)}} | ||
| + | * {{\\|128|128 (octacosahecta-core)}} | ||
| + | * {{\\|256|256 (hexapentacontadicta-core)}} | ||
| + | * {{\\|512|512 (dodecapentacta-core)}} | ||
* {{\\|1000|1000 (kilo-core)}} | * {{\\|1000|1000 (kilo-core)}} | ||
| − | * {{\\| | + | * {{\\|1024|1024 (tetracosakilia-core)}} |
}} | }} | ||
Revision as of 01:13, 21 February 2019
A chip multiprocessor (CMP) or multi-core architecture is a logic design architecture whereby multiple processing units (e.g., CPU cores) are integrated onto a single monolithic integrated circuit or onto multiple dies in a single package.
Contents
History
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Overview
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Heterogeneous multi-core architectures
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Single and Multi-ISA designs
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Multi-core chips
- 2 (dual-core)
- 3 (tri-Core)
- 4 (quad-core)
- 5 (penta-core)
- 6 (hexa-core)
- 7 (hepta-core)
- 8 (octa-core)
- 9 (nona-core)
- 10 (deca-core)
- 11 (undeca-core)
- 12 (dodeca-core)
- 13 (trideca-core)
- 14 (tetradeca-core)
- 15 (pentadeca-core)
- 16 (hexadeca-core)
- 17 (heptadeca-core)
- 18 (octadeca-core)
- 19 (nonadeca-core)
- 20 (icosa-core)
- 21 (henicosa-core)
- 22 (docosa-core)
- 23 (tricosa-core)
- 24 (tetracosa-core)
- 25 (pentacosa-core)
- 26 (hexacosa-core)
- 27 (heptacosa-core)
- 28 (octacosa-core)
- 29 (nonacosa-core)
- 30 (triaconta-core)
- 32 (dotriaconta-core)
- 40 (tetraconta-core)
- 46 (hexatetraconta-core)
- 48 (octatetraconta-core)
- 64 (tetrahexaconta-core)
- 128 (octacosahecta-core)
- 256 (hexapentacontadicta-core)
- 512 (dodecapentacta-core)
- 1000 (kilo-core)
- 1024 (tetracosakilia-core)
See also
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