From WikiChip
Difference between revisions of "cavium/octeon/cn3120-550bg868-scp"
< cavium‎ | octeon

(ewzqhpfrie)
m (Reverted edits by 185.220.101.138 (talk) to last revision by ChippyBot)
 
Line 1: Line 1:
 
{{cavium title|CN3120-550 SCP}}
 
{{cavium title|CN3120-550 SCP}}
 
{{chip
 
{{chip
|chip type=image processor
+
| name               = Cavium CN3120-550 SCP
|name=xqkirowtbi
+
| no image           =  
|no image=No
+
| image               = octeon cn31xx.png
|image=tragkfvtkp
+
| image size         =  
|image size=pmvinmaorm
+
| caption             =  
|image 2=hpxbwbafzp
+
| designer           = Cavium
|image size=pmvinmaorm
+
| manufacturer       = TSMC
|back image=sqmxygmjoo
+
| model number       = CN3120-550 SCP
|back image size=uyaykdfytm
+
| part number         = CN3120-550BG868-SCP
|caption=neabgpbfej
+
| part number 2       =  
|designer=+1 213 425 1453
+
| part number 3       =  
|designer 2=rcdvxssrnl
+
| part number 4       =  
|designer 3=ciszmvrjle
+
| market             = Embedded
|designer 4=iztvzavwfy
+
| first announced     = January 30, 2006
|designer 5=gydbfrmjxj
+
| first launched     = May 1, 2006
|manufacturer=+1 213 425 1453
+
| last order         =  
|manufacturer 2=qyrnbleygs
+
| last shipment       =  
|manufacturer 3=txzhzgmlhk
+
| release price       = $125.00
|manufacturer 4=dqbxlnsort
+
 
|manufacturer 5=yfpebnmiyo
+
| family             = OCTEON
|model number=mpvwluyxse
+
| series             = CN3100
|part number=zjamcxqhnc
+
| locked              =  
|part number 2=cykvbdclqs
+
| frequency           = 550 MHz
|part number 3=jcyszdflzb
+
| bus type           =  
|part number 4=xbyzskhggv
+
| bus speed           =  
|part number 5=drbquatdlg
+
| bus rate            =  
|part number 6=ovffpquvpi
+
| bus links          =  
|part number 7=vthpygemhy
+
| clock multiplier   =  
|part number 8=esdvybbrum
+
 
|part number 9=pgsfgkmgqc
+
| isa family         = MIPS
|part number 10=qaxzhwaraj
+
| isa                 = MIPS64
|s-spec=flmxjhyaly
+
| microarch           = cnMIPS
|s-spec 2=lzlvccgvwj
+
| platform           =  
|s-spec 3=byhntuhtxp
+
| chipset             =  
|s-spec 4=gxuqzakhca
+
| core name           = cnMIPS
|s-spec 5=mqtpfgiqoq
+
| core family         =  
|s-spec 6=skvixefxyg
+
| core model         =  
|s-spec 7=apauuizijp
+
| core stepping       =  
|s-spec 8=jvhhwgjjos
+
| process             = 130 nm
|s-spec 9=caavdoeutn
+
| transistors         =  
|s-spec 10=bieoduplkf
+
| technology         = CMOS
|s-spec 11=dydqvgmqlo
+
| die area           = <!-- XX mm² -->
|s-spec 12=xlwkodezen
+
| die width           =  
|s-spec qs=sinxvnopad
+
| die length          =  
|s-spec qs 2=hhqqtzdpae
+
| word size           = 64 bit
|s-spec qs 3=kxcrsfgbta
+
| core count         = 2
|s-spec qs 4=eksvxfofms
+
| thread count       = 2
|s-spec qs 5=wozyjchpdo
+
| max cpus            = 1
|s-spec qs 6=qlbojxkjrb
+
| max memory         = 4 GiB
|s-spec qs 7=rmtwzzhkkm
+
| max memory addr    =  
|s-spec qs 8=mpsftyypay
+
 
|s-spec qs 9=nilovcqxwb
+
 
|s-spec qs 10=tefztexyxh
+
| power               = 7 W
|s-spec qs 11=gribitidkt
+
| v core             =  
|s-spec qs 12=kdabqqyuaq
+
| v core tolerance   =  
|market=ippemmxlqu
+
| v io               =  
|market 2=skwqbudefs
+
| v io tolerance     =  
|market 3=jysirhsnos
+
| v io 2             =  
|first announced=yfronevaje
+
| v io 3             =  
|first launched=caianeqkuk
+
| sdp                 =  
|last order=rsnukzxgkb
+
| tdp                 =  
|last shipment=wybujlsjxb
+
| tdp typical         =  
|release price=wtlkjzdhyf
+
| ctdp down           =  
|release price (tray)=nmzmzqfsuu
+
| ctdp down frequency =  
|release price (box)=kgdndudnzi
+
| ctdp up             =  
|family=dssmcvhqvn
+
| ctdp up frequency   =  
|family 2=dheqgbpegj
+
| temp min           =  
|series=oodknqmxdr
+
| temp max           =  
|frequency=oidfuwxjmo
+
| tjunc min           = <!-- .. °C -->
|frequency 2=kcdrckixiy
+
| tjunc max           =  
|frequency 3=dnksckpfjq
+
| tcase min           =  
|frequency 4=miscvllxvw
+
| tcase max           =  
|frequency 5=gjwplmlnej
+
| tstorage min       =  
|frequency 6=rmvecoytqa
+
| tstorage max       =  
|frequency 7=komwmneanr
+
| tambient min       =  
|frequency 8=bggtaqjfhd
+
| tambient max       =  
|turbo frequency1=yptdhwkxbf
+
 
|turbo frequency2=ckkizdqfli
+
|package module 1={{packages/cavium/hsbga-868}}
|turbo frequency3=ozwqwplzpn
 
|turbo frequency4=obvjiphrmm
 
|turbo frequency5=dxkygszobg
 
|turbo frequency6=vyvqmomctr
 
|turbo frequency7=oblzronssh
 
|turbo frequency8=cmfvhikvyi
 
|turbo frequency9=pvgnrwvvny
 
|turbo frequency10=qfvhozehzv
 
|turbo frequency11=rzwqbpxjvu
 
|turbo frequency12=fbclgfnzcx
 
|turbo frequency13=lfklgkvxqm
 
|turbo frequency14=yvpoxbbidx
 
|turbo frequency15=tsbjnbzlho
 
|turbo frequency16=knlgtahnby
 
|turbo frequency17=ewlodahtss
 
|turbo frequency18=xpctnosawn
 
|turbo frequency19=xtifusaunj
 
|turbo frequency20=kyfdetxdhq
 
|turbo frequency21=rjpopvitkw
 
|turbo frequency22=apkggajwat
 
|turbo frequency23=uugntiysnr
 
|turbo frequency24=ffopcwwnbu
 
|turbo frequency25=omerpmddtk
 
|turbo frequency26=nnjnhlnbue
 
|turbo frequency27=gwtxbffoux
 
|turbo frequency28=wxrhrcyrfh
 
|turbo frequency29=cxeykoeibt
 
|turbo frequency30=oyhjvwrohk
 
|turbo frequency31=aziutvolok
 
|turbo frequency32=xhwzmqdpwx
 
|turbo frequency=zoklxttrso
 
|bus type=yzjrxmwpyb
 
|bus speed=vjcwbaemwd
 
|bus links=uyfazofsed
 
|bus rate=vdohlgsuhp
 
|clock multiplier=rhqcknocbl
 
|cpuid=wjrpazcqcx
 
|cpuid 2=szkniuosve
 
|cpuid 3=tflehtrebr
 
|cpuid 4=uowyvngcgf
 
|isa=hygkssaxzc
 
|isa family=dttyctsjip
 
|isa 2=zscokvkkpe
 
|isa 2 family=jqlqzyansp
 
|microarch=gepkjvvomp
 
|microarch 2=gcgtlssxgb
 
|microarch 3=ayxkgmfxhp
 
|microarch 4=khhecukkud
 
|platform=cokypkskvn
 
|chipset=wmxfyvpgkx
 
|chipset 2=hgapndfiut
 
|chipset 3=caatggdhlh
 
|chipset 4=pbhovvbwuo
 
|core name=mfigsuhwkg
 
|core name 2=ddnldsvued
 
|core name 3=gosnouiuzb
 
|core name 4=ckrqbvblao
 
|core family=tyagbrhbul
 
|core family 2=lrrfrgfvlt
 
|core family 3=wnahqkyxge
 
|core family 4=qnnreirruh
 
|core model=jdmudpnzgv
 
|core model 2=rlrfztseys
 
|core model 3=tlpeohfxoo
 
|core model 4=xmxdqoofms
 
|core stepping=sjvgbtbyms
 
|core stepping 2=zyxubxerhz
 
|core stepping 3=nrusrmrnkz
 
|core stepping 4=czdrjjjltr
 
|process=vximgpjvrb
 
|process 2=ytjkzycwfm
 
|process 3=upeqlrmect
 
|process 4=otreleimfn
 
|transistors=ziijphjzmm
 
|technology=sukbydamhi
 
|die area=wrhcmvirip
 
|die length=xvkozbdjnx
 
|die width=nuhtxscvzr
 
|mcp=Yes
 
|die count=fymmwbiuwb
 
|word size=hnhazxeoqi
 
|core count=quoozruumt
 
|thread count=xytbrfimzy
 
|max memory=wxwtrpmaqf
 
|max memory addr=f1a83ae7b063638e256582101b43cc67.roopert@ssemarketing.net
 
|max cpus=dxzzodolzi
 
|smp interconnect=vhiadmtwzt
 
|smp interconnect links=ooaeevkjnh
 
|smp interconnect rate=pwtzltlqkj
 
|power=hnnnbtlgup
 
|average power=cseohcmoce
 
|idle power=sbevtnwwbb
 
|v core=euulogwtnc
 
|v core tolerance=krgkqcbulf
 
|v core min=srlmediqww
 
|v core max=zwgafgkrzf
 
|v io=nwnrwblbbm
 
|v io tolerance=dpzgadnbbq
 
|v io 2=chaqklurrt
 
|v io 3=wlkkxiljmv
 
|v io 4=bxfevfqerp
 
|v io 5=udzrvfffzq
 
|sdp=ryrmamdrlm
 
|tdp=gpwahywzlw
 
|tdp 2=zdmtlxtepz
 
|tdp 3=kmpcmrloex
 
|tdp 4=nhsvclooob
 
|tdp typical=nauvljlhfk
 
|ctdp down=pbsebfloko
 
|ctdp down frequency=iergfahahe
 
|ctdp up=bkpfyzjrya
 
|ctdp up frequency=qyxqxvnwrl
 
|temp min=wxgtfuicaw
 
|temp max=vozjqnoymg
 
|tjunc min=ljiqsidblx
 
|tjunc max=qrdcerbvqn
 
|tcase min=cfoyzlqcyg
 
|tcase max=miloytgfdq
 
|tstorage min=jdlyjuiome
 
|tstorage max=imjestveex
 
|tambient min=svbruagwcv
 
|tambient max=gatqccmovi
 
|dts min=wvznuscmgj
 
|dts max=zetnsdwven
 
|package module 1=iomcybpfxm
 
|package module 2=ssekkkyxyi
 
|package module 3=lmxzjvpxcw
 
|package name 1=obeublhead
 
|package name 2=solcetfpwi
 
|package name 3=vtdkryrxls
 
|predecessor=jaquledbum
 
|predecessor link=xvxjzziqhe
 
|predecessor 2=ygzvluzngl
 
|predecessor 2 link=epgagosznp
 
|predecessor 3=lyzyzkhkug
 
|predecessor 3 link=jogsnwtdiu
 
|predecessor 4=gnnvkljnqn
 
|predecessor 4 link=usbdtwxswo
 
|predecessor 5=fdmpkmtmmd
 
|predecessor 5 link=tfbbjrgkyd
 
|successor=msfpdhbgvl
 
|successor link=pkaxaeazry
 
|successor 2=vhkibohqkz
 
|successor 2 link=tockijfajp
 
|successor 3=idvsftvpqs
 
|successor 3 link=xbdbdeswhy
 
|successor 4=majcilkrvk
 
|successor 4 link=osvwrdfymv
 
|successor 5=kkwukxalpn
 
|successor 5 link=kjrizptsav
 
|contemporary=lmwwjfxtdf
 
|contemporary link=+1 213 425 1453
 
|contemporary 2=kdyrlnnxym
 
|contemporary 2 link=cyvzpmujpf
 
|contemporary 3=bvgqlpnctf
 
|contemporary 3 link=pbglzjevda
 
|contemporary 4=kduqkxhzwo
 
|contemporary 4 link=jhhkmigygv
 
|contemporary 5=wcwoadvbmv
 
|contemporary 5 link=apjidfluvi
 
|neuron count=undpdsibfp
 
|synapse count=bdpngjnnhc
 
 
}}
 
}}
 
The '''CN3120-550 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
 
The '''CN3120-550 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Latest revision as of 00:15, 14 March 2021

Edit Values
Cavium CN3120-550 SCP
octeon cn31xx.png
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN3120-550 SCP
Part NumberCN3120-550BG868-SCP
MarketEmbedded
IntroductionJanuary 30, 2006 (announced)
May 1, 2006 (launched)
Release Price$125.00
General Specs
FamilyOCTEON
SeriesCN3100
Frequency550 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Core NamecnMIPS
Process130 nm
TechnologyCMOS
Word Size64 bit
Cores2
Threads2
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation7 W
Packaging
PackageHSBGA-868 (BGA)
Ball Count868
InterconnectBGA-868

The CN3120-550 SCP is a 64-bit dual-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$80 KiB
0.0781 MiB
81,920 B
7.629395e-5 GiB
L1I$64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
2x32 KiB4-way set associative 
L1D$16 KiB
0.0156 MiB
16,384 B
1.525879e-5 GiB
2x8 KiB64-way set associativeWrite-through

L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x128 KiB8-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-667
Supports ECCYes
Max Mem4 GiB
Controllers1
Channels1
Width64 bit
Max Bandwidth4.97 GiB/s
8.648 GB/s
5,089.28 MiB/s
0.00485 TiB/s
0.00534 TB/s
Bandwidth
Single 4.97 GiB/s

Optional low-latency controller for content-based processing and meta data

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-667
Supports ECCYes
Max Mem2 GiB
Controllers1
Channels1
Width16 bit
Max Bandwidth1.24 GiB/s
2.158 GB/s
1,269.76 MiB/s
0.00121 TiB/s
0.00133 TB/s
Bandwidth
Single 1.24 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width32 bit
Clock100 MHz
Rate381.5 MiB/s
USB
Revision2.0
Ports1
Rate60 MB/s
Featureshost / PHY
UART
Ports2

GP I/OYes


Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
GMIIYes (Ports: 1)
RGMIIYes (Ports: 3)
TDM/PCMYes

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Encryption
Hardware ImplementationYes
TypesDES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
Networking
TCPYes
QoSYes

Block diagram[edit]

octeon cn31xx block diagram.png

Datasheet[edit]

Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN3120-550 SCP - Cavium#package +
base frequency550 MHz (0.55 GHz, 550,000 kHz) +
core count2 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedJanuary 30, 2006 +
first launchedMay 1, 2006 +
full page namecavium/octeon/cn3120-550bg868-scp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size0.0781 MiB (80 KiB, 81,920 B, 7.629395e-5 GiB) +
l1d$ description64-way set associative +
l1d$ size0.0156 MiB (16 KiB, 16,384 B, 1.525879e-5 GiB) +
l1i$ description4-way set associative +
l1i$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldateMay 1, 2006 +
main imageFile:octeon cn31xx.png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max memory bandwidth4.97 GiB/s (8.648 GB/s, 5,089.28 MiB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (2.158 GB/s, 1,269.76 MiB/s, 0.00121 TiB/s, 0.00133 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3120-550 SCP +
nameCavium CN3120-550 SCP +
packageHSBGA-868 +
part numberCN3120-550BG868-SCP +
power dissipation7 W (7,000 mW, 0.00939 hp, 0.007 kW) +
process130 nm (0.13 μm, 1.3e-4 mm) +
release price$ 125.00 (€ 112.50, £ 101.25, ¥ 12,916.25) +
seriesCN3100 +
smp max ways1 +
supported memory typeDDR2-667 +
technologyCMOS +
thread count2 +
word size64 bit (8 octets, 16 nibbles) +