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Difference between revisions of "arm holdings/microarchitectures/neoverse n1"
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* [[7 nm process]]
 
* [[7 nm process]]
 
{{expand list}}
 
{{expand list}}
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== Die ==
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=== N1 core ===
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* [[7 nm process]]
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* 1 Core + L2
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* 1.2 mm² die size (1C + 512 KiB L2)
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* 1.4 mm² die size (1C + 1 MiB L2)
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* 1 W @ 2.6 GHz (0.75 V), 1.8 W @ 3.1 W (1.0 V)
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:[[File:neoverse n1 core die plot.png|600px]]
  
 
== Bibliography ==
 
== Bibliography ==
 
* Drew Henry keynote, TechCon 2018 keynote.
 
* Drew Henry keynote, TechCon 2018 keynote.
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* Drew Henry, direct communication
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* Most of the technical details were obtained directly from Arm

Revision as of 12:54, 20 February 2019

Edit Values
Ares µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionFebruary 20, 2019
Process7 nm
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Succession

Neoverse N1 (codename Ares) is a high-performance ARM microarchitecture designed by ARM Holdings for the server market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

History

Arm's server roadmap.

Ares was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote. Ares was officially unvailed on February 20, 2019.

Release Dates

Ares was officially disclosed on February 20, 2019.

Process Technology

Ares specifically takes advantage of the power and area advantages of the 7 nm process.

Architecture

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

This list is incomplete; you can help by expanding it.

Die

N1 core

  • 7 nm process
  • 1 Core + L2
  • 1.2 mm² die size (1C + 512 KiB L2)
  • 1.4 mm² die size (1C + 1 MiB L2)
  • 1 W @ 2.6 GHz (0.75 V), 1.8 W @ 3.1 W (1.0 V)


neoverse n1 core die plot.png

Bibliography

  • Drew Henry keynote, TechCon 2018 keynote.
  • Drew Henry, direct communication
  • Most of the technical details were obtained directly from Arm
codenameAres +
designerARM Holdings +
first launchedFebruary 20, 2019 +
full page namearm holdings/microarchitectures/neoverse n1 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameAres +
process7 nm (0.007 μm, 7.0e-6 mm) +