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'''Cortex-M55''' is an ultra-low-power [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for microcontrollers and embedded subsystems. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-M55, which implements the {{arm|ARMv8.1-M}} ISA, is an ultra-low-power core which is often found in microcontrollers, low-power chips, and in the embedded subsystems of more powerful chips.

The Cortex-M55 is designed to be fabricated on various different [[process nodes]] ranging from very mature nodes such as the [[130 nm]] to leading-edge [[7 nm]] and [[5 nm]] nodes.

:[[File:cortex-m55 block diagram.svg|850px]]

The Cortex-M55 is a synthesizable ultra-low-power core designed by [[Arm]] for an array of applications such as microcontrollers and embedded subsystems doing background work on more performant SoCs. Successionally and architecturally, the Cortex-M55 is the successor to the {{\\|Cortex-M7}} and the {{\\|Cortex-M4}}, although in purely raw performance it's slightly behind the M7, though it makes up for it in new technologies such as its {{arm|Helium|new vector extension}}. The Cortex-M55 is said to deliver 1.6 [[Dhrystone DMIPS/MHz]] and 4.2 [[CoreMark/MHz]] which is about 25% higher than the {{\\|Cortex-M4|M4}} but about 20% lower than the {{\\|Cortex-M7|M7}}. In terms of frequency, the M55 is said to deliver up to 15% higher clock speed over the {{\\|Cortex-M4|M4}}.

 

=== Configuration ===

 

 

== Pipeline ==

 

 

 

 

 

=== Extended processing pipeline ===

 

When the {{arm|Helium}} extension is present, it reuses the FPU registers as vector registers, each being 128-bit wide. Internally, the vector unit is implemented with a 64-bit data path. This is twice as wide as prior Cortex-M designs but half the width of the ISA operations, therefore each operation takes two clock cycles to complete. The architecture permits overlapping execution cycles between instructions which are taken advantage of by the Cortex-M55, therefore when overlapping memory access and data processing operations together, both operations can be carried out in parallel.

 

 

 

The TCM subsystem is somewhat similar to the one found in the {{\\|Cortex-M7}} but comes with a few noticeable differences. The TCM consists of an instruction TCM (I-TCM) and a data TCM (D-TCM). As with the {{\\|Cortex-M7|M7}}, the purpose of the TCM subsystem is to provide deterministic latencies for real-time applications. The instruction TCM is optional and configurable from 0 to 16 MiB with optional ECC support. It is 32-bit wide, allowing up to 4 bytes per cycle to be transferred from the I-TCM to either the [[instruction fetch]] or the [[instruction memory]]. The D-TCM is also optional and is configurable from 0 to 16 MiB in capacity with optional ECC support. Whereas the {{\\|Cortex-M7}} featured two 32-bit data TCM interfaces, the M55 features four 32-bit data TCM interfaces which are split equally using address bits[3:2]. The data TCM interfaces collectively have an aggregated bandwidth of 128-bit per cycle, however since the Helium vector extension features an interface data path of 64-bit, software execution can only generate 64-bit data transfers per cycle. The rest of the bandwidth can be used for other purposes such as data memory access operations, transferring data from and to the TCM simultaneously while the data is read by the core execution. Accesses to TCM memory banks are prioritized for software execution, therefore an attempt by the DMA controller will be stalled while the software is reading from the same TCM bank.