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Difference between revisions of "arm holdings/microarchitectures/cortex-a75"
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{{armh title|Cortex-A75|arch}}
 
{{microarchitecture
 
|atype=CPU
 
|name=Cortex-A75
 
|designer=ARM Holdings
 
|manufacturer=TSMC
 
|introduction=May 29, 2017
 
|process=16 nm
 
|process 2=14 nm
 
|process 3=10 nm
 
|process 4=7 nm
 
|cores=1
 
|cores 2=2
 
|oooe=Yes
 
|speculative=Yes
 
|renaming=Yes
 
|stages min=11
 
|stages max=13
 
|decode=3-way
 
|isa=ARMv8.2
 
|feature=Hardware virtualization
 
|extension=FPU
 
|extension 2=NEON
 
|l1i=8-64 KiB
 
|l1i per=core
 
|l1i desc=4-way set associative
 
|l1d=8-64 KiB
 
|l1d per=core
 
|l1d desc=4-way set associative
 
|l2=64-256-512 KiB
 
|l2 per=core
 
|l3=0-4 MiB
 
|l3 per=Cluster
 
|predecessor=Cortex-A73
 
|predecessor link=arm_holdings/microarchitectures/cortex-a73
 
|successor=Cortex-A76
 
|successor link=arm_holdings/microarchitectures/cortex-a76
 
}}
 
'''Cortex-A75''' (codename '''Prometheus''') is the successor to the {{armh|Cortex-A73|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A75, which implemented the {{arm|ARMv8.2}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A55}}) in a {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance.
 
  
== Compiler support ==
 
{| class="wikitable"
 
|-
 
! Compiler !! Arch-Specific || Arch-Favorable
 
|-
 
| [[Arm Compiler]] || <code>-mcpu=cortex-a75</code> || <code>-mtune=cortex-a75</code>
 
|-
 
| [[GCC]] || <code>-mcpu=cortex-a75</code> || <code>-mtune=cortex-a75</code>
 
|-
 
| [[LLVM]] || <code>-mcpu=cortex-a75</code> || <code>-mtune=cortex-a75</code>
 
|}
 
 
If the Cortex-A75 is coupled with the {{\\|Cortex-A55}} in a [[big.LITTLE]] system, GCC also supports the following option:
 
 
{| class="wikitable"
 
|-
 
! Compiler !! Tune
 
|-
 
| [[GCC]] || <code>-mtune=cortex-a75.cortex-a55</code>
 
|}
 
 
== Architecture ==
 
=== Key changes from {{\\|Cortex-A73}} ===
 
{{empty section}}
 
=== Block Diagram ===
 
{{empty section}}
 
=== Memory Hierarchy ===
 
{{empty section}}
 

Revision as of 18:48, 23 March 2020

codenameCortex-A75 +
core count1 + and 2 +
designerARM Holdings +
first launchedMay 29, 2017 +
full page namearm holdings/microarchitectures/cortex-a75 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A75 +
pipeline stages (max)13 +
pipeline stages (min)11 +
process16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) +