Revision as of 00:40, 12 December 2023

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AWS Graviton4

General Info

Microarchitecture

AWS Graviton4 (Alpine ALC14C00) is a hexanonaconta-core ARMv9 multiprocessor designed by Amazon (Annapurna Labs) for Amazon's own infrastructure. Graviton4 is a 5 nm(?) 7-chiplet design SoC based on the Arm CMN-700 mesh interconnect and Neoverse V2 core microarchitecture. This chip supports dodeca-channel DDR5-5600 ECC memory along with 96 lanes of PCIe 5.0.

Overview

This 4th-generation server processor was first announced during Amazon's AWS re:Invent 2023 by Adam Selipsky in his keynote. The general rollout for the Graviton4 chip in the AWS data center occurred in early 2024. These processors are offered as part of Amazon's EC2 instances.

Graviton4 features a 7-chiplet design similar to its predecessor, Graviton3. This chip features 96 cores, 50% more than the prior generation. The core implementation was updated to Arm's Neoverse V2 microarchitecture with 2x256b SVE support, also bringing support up to Armv9.0 ISA for the first time. The chip supports up to 12 channels for DDR5 ECC DIMMs with data rates of up to 5600 MT/s. The Graviton4 tripled the number of PCIe lanes to 96 lanes of PCIe 5.0.

The Graviton4 is the first chip from the Graviton family to feature multiprocessing support. The chip introduced dual-socket support with full coherency for up to 192 vCPUs and DDR5 channels on a single server. The Graviton4 also expanded encryption support to the new multi-socket coherency links as well as to the Nitro cards interfaces. The full platform can be configured to run in a number of modes that can potentially offer additional power saving: two non-coherent virtual systems, one coherent virtual system, two metal systems, or one metal system.

Packaging

The Graviton4 features a 7-chiplet architecture similar in design to the Graviton3. The compute SoC die sits in the middle with 4 DDR memory controller dies and 2 PCIe controller dies. Each DDR memory controller features support for 3 memory channels - two dies to the east and two dies to the west for a total of 6 memory channels on each side. There are two PCIe controller dies - one to the north and one to the south of the chip. The four DDR memory controller dies are interconnected with the SoC via embedded silicon bridges in the package.Unlike the Graviton3, the two PCIe controller dies are not abutting the compute SoC die and are no longer controller via an embedded bridge in the package.

Cache

Main article: Neoverse V2 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 12 MiB 12,288 KiB 12,582,912 B L1I$ 6 MiB 6,144 KiB 6,291,456 B 96x64 KiB     L1D$ 6 MiB 6,144 KiB 6,291,456 B 96x64 KiB     L2$ 192 MiB 196,608 KiB 201,326,592 B 0.188 GiB     96x2 MiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR5-5600 Supports ECC Yes Controllers 4 Channels 12 Max Bandwidth 537.6 GB/s 500.679 GiB/s 512,695.313 MiB/s 537,600 MB/s 0.489 TiB/s 0.538 TB/s Bandwidth Single 44.8 GB/s Double 89.6 GB/s Quad 179.2 GB/s Octa 358.4 GB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
	PCIe Revision 5.0 Max Lanes 96 Configs x16, x8, x4