Editing amd/packages/socket strx4

{{amd title|Socket sTRX4}}
{{package
|name=Socket sTRX4
|designer=AMD
|market=HEDT
|first launched=November 25, 2019
|microarch=Zen 2
|tdp=280 W
|package name=sTRX4
|package name 2=FCLGA-4094
|package type=FC-OLGA
|package contacts=4094
|package dimension=75.40 mm
|package dimension 2=58.50 mm
|package dimension 3=6.26 mm
|package pitch=0.87 mm
|package pitch 2=1.00 mm
|socket type=SM-LGA
|socket name=sTRX4
|predecessor=Socket TR4
|predecessor link=amd/packages/socket tr4
|contemporary=Socket sWRX8
|contemporary link=amd/packages/socket swrx8
|contemporary 2=Socket SP3
|contemporary 2 link=amd/packages/socket sp3
}}
'''Socket sTRX4''' is a microprocessor socket designed by [[AMD]] for their third generation {{amd|Ryzen Threadripper}} high end desktop processors, the successor to {{\\|Socket TR4}}. Contemporary mainstream desktop, workstation, and server processors use {{\\|Socket AM4}}, {{\\|Socket sWRX8|sWRX8}}, and {{\\|Socket SP3|SP3}} respectively.

Socket sTRX4 is mechanically identical and almost pin-compatible to Socket SP3 and the sockets TR4 and sWRX8 also derived from it, but differs by the number of memory channels and I/O interfaces available: SP3 processors use [[DDR4]] {{abbr|RDIMM}}s on up to eight memory channels, sWRX8 processors {{abbr|UDIMM}}s or RDIMMs, while TR4 and sTRX4 processors support only UDIMMs on up to four memory channels. TR4 and sTRX4 omit four of eight PCIe interfaces present on Socket SP3 and sWRX8, but TR4 processors also pin out four additional USB ports and a {{abbr|HDA}} interface which are not supported by the other infrastructures.

While sTRX4 processors were designed to be backwards compatible with Socket TR4<!--AMD-55803, AMD-55898--> they are not supported on first generation Threadripper motherboards, nor are TR4 processors accepted on sTRX4 boards. sTRX4 processors are also not supported in Socket SP3 and sWRX8 or vice versa.

== Overview ==
Socket sTRX4 is a zero insertion force, screw actuated, [[wikipedia:Surface-mount technology|surface-mount]] [[land grid array]] socket for use with a 4094-contact, 1.00&nbsp;mm × 0.87&nbsp;mm interstitial pitch, organic land grid array CPU package.

This single socket client infrastructure supports four channels of 72-bit [[DDR4]] memory with up to two {{abbr|UDIMM}}s per channel, four 16-lane PCIe Gen 4 I/O links, four USB 3.2 Gen 2 ports, and up to 16 SATA Gen 3 ports. 8-layer motherboards are required to route these signals. 

The following AMD processor families use Socket sTRX4:
{| class="wikitable"
! || CPU Family || Microarch. || Process || Products
|-
|Type 1
|{{amd|CPUID#Family 23 (17h)|Family 17h}} Models 30h–3Fh
|{{amd|Zen 2|l=arch}}
|[[7&nbsp;nm]] & [[12&nbsp;nm]]<!--https://www.amd.com/en/product/9111-->
|Ryzen Threadripper 3900 "{{amd|Castle Peak|l=core}}" (Model 31h)
|-
|Type 2
|{{amd|CPUID#Family 25 (19h)|Family 19h}} Models 00h–0Fh
|{{amd|Zen 3|l=arch}}
|[[7&nbsp;nm]] & [[12&nbsp;nm]](?)
|<!--(Model 08h)-->
|}

The codename of AMD's sTRX4 reference platform ({{abbr|CRB}}) is "Sharkstooth".

== Package Description ==
The sTRX4 CPU package is lidded, has a 58.50&nbsp;mm × 75.40&nbsp;mm organic substrate with [[flip chip]] die attachment, and 4094 nickel and gold plated land pads. It ships with a carrier frame pre-installed. The carrier frame, made from an orange colored polycarbonate material, is a part of the package loading mechanism and remains on the package in the socket.

The package substrate has six keying notches along the short edges preventing it from being inserted 180 degrees rotated into the carrier frame or socket, or in an incompatible socket with mismatching keying features. Four additional positions are reserved for future models. However all sockets SP3, TR4, sTRX4, and sWRX8, and all processors for these sockets have the same keying. It is worth noting that these processors are also electrically keyed by pin {{\\|Socket SP3#SP3R1|SP3R1 and SP3R2}}. To boot the processor the motherboard must also provide compatible firmware. A triangular symbol on both sides of the substrate marks the location of pin A1, with corresponding markings on the socket. [[wikipedia:Decoupling capacitor|Decoupling capacitors]] are placed under the lid around the chiplets on the top side, and in two windows in the pad grid on the bottom side.

sTRX4 is a [[multi-chip package]] integrating one I/O die and 4 or 8 Core Complex Dies which contain eight CPU cores each. The CCDs closer to the IOD are populated first. The I/O die contains eight memory controllers, eight 16-lane multi-function I/O interfaces, and other I/O facilities. The silicon in sTRX4 processors is "Starship" rev. SSP-B0.<!--AMD-56323-0.78 RG 17h 30-3Fh--> AMD used the same chips for EPYC 7002 server and embedded processors, and Ryzen Threadripper workstation processors; see {{amd|CPUID#Family 23 (17h)|CPU Family 17h}}.

[[file:Socket sTRX4 routing.svg|left]] The diagram on the left (top view, not to scale) shows the routing of high speed signals between the dies and the package contacts. Eight {{abbr|IF:CCM}} blocks extend the Data Fabric on the IOD to the CCDs, each driving a {{abbr|GMI}}2 physical link routed on two package layers. AMD chose not to route these signals on a 2.5D interposer or [[EMIB]] for reasons of product flexibility and reach.<!--Burd2018, Naffziger2020--> SSP-B0 CCDs contain two {{abbr|CCX}}s with 16&nbsp;MiB L3 cache each, the GMI2 port and its die bumps are located in the center of the die to reduce memory latency from the L3 cache.<!--Naffziger2020--> GMI2 links are serial, single-ended links with 31 transmit (to IOD) and 39 receive lanes, one clock gating lane per direction, and a differential pair of clock lanes. They use customized 10:1 {{abbr|SerDes}} running at {{abbr|FCLK|Infinity Fabric clock}}, so for instance a 1.46&nbsp;GHz FCLK coupled to the bus clock of DDR4-2933 SDRAM gives a raw data rate of 14.6&nbsp;GT/s per lane or 71.2&nbsp;GB/s per link from IOD to CCD. Not shown are eight {{abbr|TWIX}} ports which extend the Control Fabric to the CCDs, these links run on four data and two clock lanes, as well as USB signals and low speed busses.<!--AMD-55803 PPR SSP-B0, Singh2020, Naffziger2020--> For details and the IOD internal topology see AMD {{amd|Infinity Fabric}}. {{clear}}

sTRX4 packages are not merely reconfigured EPYC processors, they support memory and I/O interfaces on the same pins as {{\\|Socket TR4}} processors and the signal routing on the package differs from {{\\|Socket SP3}} and {{\\|Socket sWRX8|sWRX8}} packages in the following ways:

* Only four of the eight DRAM channels A-H are usable, namely A, D, E, and H, connected to {{abbr|UMC}}2, 3, 4, and 5 on the IOD.<!--AMD-56515 FDS sTRX4/sWRX8 Tbl 37--> {{abbr|UDIMM}}s are supported, but not {{abbr|RDIMM}}s. Memory up to DDR4-3200 (not overclocked) is supported, TR4 processors are rated for up to DDR4-2933 memory.

* Only four of the eight 16-lane I/O interfaces P0-P3 and G0-G3 are usable, namely P0, P2, G0, and G2, connected to SerDes P1, P3, G1, and G2 on the IOD.<!--AMD-56515 FDS sTRX4/sWRX8 Tbl 37--> All of these I/O interfaces can be configured as PCIe link, some lanes alternatively as SATA link. The {{abbr|xGMI}}, S-Link, and XGBE protocols are not supported on this socket. (The cache coherent xGMI links connect the Data Fabrics of each processor on dual socket systems. S-Link is a cache coherent link to {{abbr|CCIX}} memory expanders. XGBE is a backplane Ethernet link with data rates up to 10&nbsp;Gbit/s.) TR4 processors do not support PCIe Gen 4.

* SATA is an alternative function on the P0, P1, G2, and G3 interfaces so only 16 of the 32 SATA links are usable.

* The {{abbr|WAFL}} interface is not supported on this socket, or on Socket TR4 or sWRX8.

== Socket Description ==
Socket sTRX4 is mechanically identical to {{\\|Socket SP3#Socket Description|Socket SP3}}.

== Features ==
* Lidded [[land grid array]] package, 75.40&nbsp;mm × 58.50&nbsp;mm
** 4094 contacts in a 82 × 55 grid with 0.87&nbsp;mm × 1.00&nbsp;mm interstitial pitch
** Organic substrate, [[flip chip]] die attachment

* 4 × 64/72 bit DDR4 SDRAM interface
** Up to 1600&nbsp;MHz, PC4-25600 (DDR4-3200), 102.4&nbsp;GB/s total raw bandwidth, not overclocked
** Up to 2 DIMMs/channel, up to 8 DIMMs total
** {{abbr|SR}}/{{abbr|DR}} {{abbr|UDIMM}} types only
** ECC supported
** Memory addressing up to 1&nbsp;TiB/channel<!--AMD-56443-->
** Max. total memory capacity 256&nbsp;GiB using eight 32&nbsp;GiB DIMMs

* Four multi-function I/O interfaces P0, P2, G0, G2
:{| class="wikitable" style="text-align:center"
|Lane||15||14||13||12||11||10||9||8||7||6||5||4||3||2||1||0
|-
|rowspan="5"|PCIe||colspan="16"|x16
|-
|colspan="8"|x8||colspan="8"|x8
|-
|colspan="4"|x4||colspan="4"|x4||colspan="4"|x4||colspan="4"|x4
|-
|colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2
|-
|x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1
|-
|SATA||colspan="8"| ||7||6||5||4||3||2||1||0
|-
| ||colspan="4"|PHY 3||colspan="4"|PHY 2||colspan="4"|PHY 1||colspan="4"|PHY 0
|}
:* PCIe Gen 1, 2, 3, 4 (16&nbsp;GT/s) protocol supported on P0, P2, G0, G2
:** 16 lanes, up to 8 ports per interface configurable x16, x8, x4, x2, x1 with power-of-two alignment (e.g. 1x4 + 4x1 + 1x8)
:** Max. 7 PCIe ports in each 8-lane subset (e.g. 0x8 + 8x1 is not possible)
:** Max. 7 PCIe ports per interface if any lane is configured as SATA port
:** Different PCIe generations supported on the ports in the same interface
:** Lane polarity inversion, per port lane reversal
:** Up to 56 PCIe lanes total (one x8 link reserved for chipset attachment)

:* SATA Gen 1, 2, 3 (6&nbsp;Gb/s) protocol supported on the lower 8 lanes of P0 and G2
:** P0: SATA00-07, G2: SATA20-27
:** Up to 16 SATA ports total

:* Four {{abbr|PHY}} groups on each interface
:** Lanes sharing a PHY group must use the same protocol (PCIe, SATA)

* 4 × USB 1.1, 2.0, 3.2 Gen 2×1 (10&nbsp;Gb/s) ports
** Type-C connectors are supported with external components

* Low speed interfaces (some sharing pins):
** 2 × 4-wire or 4 × 2-wire {{abbr|UART}} modeled after the [[wikipedia:16550 UART|16550]]
** {{abbr|LPC}}
** 1/2/4-bit {{abbr|SPI/eSPI}} up to 100&nbsp;MHz (SPI) and 66&nbsp;MHz (eSPI)
** 6 × {{abbr|I<sup>2</sup>C}}
** 2 × {{abbr|SMBus}}
** 2 × {{abbr|SGPIO}}
** 2 × SATA {{abbr|DevSlp}}
** 70 × {{abbr|GPIO}}
** Sideband Interface ({{abbr|SB-TSI}})
** 2 × Serial VID Interface (SVI2)
** {{abbr|JTAG}}

== Chipsets ==
sTRX4 processors are {{abbr|SoC}}s with an integrated controller hub so they do not require a chipset, but are paired with the AMD {{amd|TRX40}} chipset (AMD 500-Series)<!--AMD-56724, AMD-56437--> serving as I/O expander.

The chipset is attached with an x8 PCIe link and can provide the following additional interfaces:
* 16 lanes (+ 8-lane CPU link) PCIe Gen 1, 2, 3, 4 (16&nbsp;GT/s)
* 8 × SATA Gen 1, 2, 3 (6&nbsp;Gb/s) ports sharing pins with the PCIe interface
* 4 × SATA Gen 1, 2, 3 (6&nbsp;Gb/s) ports, dedicated
* 8 × USB 1.1, 2.0, 3.2 Gen 2 (10&nbsp;Gb/s) ports
* 5 × USB 1.1, 2.0 ports 

An audio interface is not provided by Socket sTRX4 or the chipset, an audio controller is commonly attached as on-board USB device. The sTRX4/TRX40 platform supports overclocking.

== Processors using Socket sTRX4 ==
<!-- NOTE:
This table is generated automatically from the data in the actual articles.
If a microprocessor is missing from the list, an appropriate article for it needs to be
created and tagged accordingly.
Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable">
{{comp table header|cols|Family|Microarch.|Cores|Threads|L2$|L3$|Base|Turbo|Memory|{{abbr|TDP}}|Launched|Price|{{abbr|OPN}}}}
{{#ask: [[Category:microprocessor models by amd]] [[socket::~*sTRX4]]
|?full page name
|?model number
|?microprocessor family
|?microarchitecture
|?core count
|?thread count
|?l2$ size
|?l3$ size
|?base frequency#GHz
|?turbo frequency#GHz
|?supported memory type
|?tdp
|?first launched
|?release price
|?part number
|sort=model number
|format=template
|template=proc table 3
|userparam=15
|mainlabel=-
|valuesep=,<br/>
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[socket::~*sTRX4]]}}
</table>
{{comp table end}}

== Photos ==
{{empty section}}

== Package Diagram ==
[[File:LGA-4094 diag.svg]]

sTRX4 package (same as {{\\|Socket SP3}} package). All dimensions in millimeters.

== Socket Diagrams ==

== Pin Map ==
[[File:Socket SP3 pinmap.svg|800px]]

Socket sTRX4 pinout (same as {{\\|Socket SP3}}, with some {{\\|Socket SP3#Pin Description|constraints}}), top view. This is a preview, click for a larger image and other views.

=== Pin Description ===
See {{\\|Socket SP3#Pin Description|Socket SP3}}.

== Bibliography ==
* {{cite techdoc|title=Socket SP3 Design Specification|publ=AMD|pid=55260|rev=1.16|date=2020-08}}
* {{cite techdoc|title=Functional Data Sheet for sTRX4 and sWRX8 Processors|publ=AMD|pid=56515|rev=0.81|date=2019-08}}
* {{cite techdoc|title=Infrastructure Roadmap for sTRX4 and sWRX8 Processors|publ=AMD|pid=56443|rev=0.92|date=2021-07}}
* {{cite techdoc|title=Preliminary Processor Programming Reference (PPR) for AMD Family 17h Model 31h, Revision B0 Processors|publ=AMD|pid=55803|rev=0.93|date=2020-10-28}}
* {{cite techdoc|title=Revision Guide for AMD Family 17h Models 30h-3Fh Processors|publ=AMD|pid=56323|rev=0.78|date=2021-02}}
* {{cite article|authors=Burd, Thomas;Beck, Noah;White, Sean;Paraschou, Milam;Kalyanasundharam, Nathan;Donley, Gregg;Smith, Alan;Hewitt, Larry;Naffziger, Samuel|title=“Zeppelin”: An SoC for Multichip Architectures|date=2018-10-26|journal=IEEE JSSC|volume=54|issue=1|pages=133-143|doi=10.1109/JSSC.2018.2873584}}
* {{cite article|authors=Singh, Teja;Rangarajan, Sundar;John, Deepesh;Schreiber, Russell;Oliver, Spence;Seahra, Rajit;Schaefer, Alex|title=Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core|date=2020-02|conference=Proceedings of IEEE ISSCC 2020|pages=42-44|doi=10.1109/ISSCC19947.2020.9063113}}
* {{cite article|authors=Naffziger, Samuel;Lepak, Kevin;Paraschou, Milam;Subramony, Mahesh|title=AMD Chiplet Architecture for High-Performance Server and Desktop Products|date=2020-02|conference=Proceedings of IEEE ISSCC 2020|pages=44-45|doi=10.1109/ISSCC19947.2020.9063103}}
* {{cite techdoc|authors=Naffziger, Samuel|title=AMD Chiplet Architecture for High-Performance Server and Desktop Products|url=https://www.slideshare.net/AMD/amd-chiplet-architecture-for-highperformance-server-and-desktop-products|publ=IEEE ISSCC 2020|date=2020-02-17}}

== See also ==
* {{\\|Socket AM4}}
* {{\\|Socket TR4}}
* {{\\|Socket sWRX8}}
* {{\\|Socket SP3}}

[[Category:amd]]
designer	AMD +
first launched	November 25, 2019 +
instance of	package +
market segment	HEDT +
microarchitecture	Zen 2 +
name	ryzen 5 1600 +
package	sTRX4 + and FCLGA-4094 +
package contacts	4,094 +
package height	6.26 mm (0.246 in) +
package length	75.4 mm (7.54 cm, 2.969 in) +
package pitch	0.87 mm (0.0343 in) + and 1 mm (0.0394 in) +
package type	FC-OLGA +
package width	58.5 mm (5.85 cm, 2.303 in) +
socket	sTRX4 +
tdp	280 W (280,000 mW, 0.375 hp, 0.28 kW) +