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|tdp=140 W
 
|tdp=140 W
 
|package name=LGA-1944
 
|package name=LGA-1944
|package type=FC-OLGA
+
|package type=Organic Flip-Chip Land Grid Array
 
|package contacts=1944
 
|package contacts=1944
|package dimension=60.0 mm
+
|package dimension=42.5 mm
|package dimension 2=42.5 mm
+
|package dimension 2=60.0 mm
 
|package pitch=1.00 mm
 
|package pitch=1.00 mm
 
|socket name=Socket G34
 
|socket name=Socket G34
|socket type=SM-LGA
+
|socket type=LGA
 
}}
 
}}
 
'''Socket G34''' was designed for '''LGA-1944'''-packaged [[AMD]] [[amd/opteron|Opteron]] 6000 Series microprocessors optimized for performance per Watt and scalability. The designation G34 stands for AMD's third generation server socket with four memory channels. Socket G34 has a [[DDR3]] memory interface while its predecessors {{\\|Socket 940}} and {{\\|Socket F}} were designed for [[DDR]] and [[DDR2]] memory, respectively, and also offers additional [[HyperTransport]] links to improve the bandwidth and latency between nodes on multiprocessor systems. It has a smaller sibling {{\\|Socket C32}} which supports two memory channels and three HT links as the prior generations. Uniprocessor Opterons with a DDR3 interface were released in packages for {{\\|Socket AM3}} and {{\\|Socket AM3+|AM3+}} which make a single HT link available. Socket G34 was superseded by {{\\|Socket SP3}}.
 
'''Socket G34''' was designed for '''LGA-1944'''-packaged [[AMD]] [[amd/opteron|Opteron]] 6000 Series microprocessors optimized for performance per Watt and scalability. The designation G34 stands for AMD's third generation server socket with four memory channels. Socket G34 has a [[DDR3]] memory interface while its predecessors {{\\|Socket 940}} and {{\\|Socket F}} were designed for [[DDR]] and [[DDR2]] memory, respectively, and also offers additional [[HyperTransport]] links to improve the bandwidth and latency between nodes on multiprocessor systems. It has a smaller sibling {{\\|Socket C32}} which supports two memory channels and three HT links as the prior generations. Uniprocessor Opterons with a DDR3 interface were released in packages for {{\\|Socket AM3}} and {{\\|Socket AM3+|AM3+}} which make a single HT link available. Socket G34 was superseded by {{\\|Socket SP3}}.
  
The LGA-1944 package is a multi-chip module integrating two dies, each providing four 16-bit HyperTransport Gen 3 links and two DDR3 memory controllers. Each HT link can be further unganged into two independent 8-bit links. The package has 1132 signal I/O, 341 power, and 471 ground pins. Package size constrained the HT interface to 64 lanes total, one x16 and one x8 link from node 0, two x16 links and one x8 link from node 1. One x16 link on node 0 is not connected, the remaining links connect the nodes in the package. Each link can be used for I/O, e.g. connecting a GPU through a HT-PCI bridge, or for cache coherent inter-socket traffic using an AMD proprietary protocol, with flexible routing permitting various network topologies on 2P and 4P systems. 8P systems were not considered due to insufficient demand.
+
The LGA-1944 package is a multi-chip module integrating two dies, each providing four 16-bit HyperTransport Gen 3 links and two DDR3 memory controllers. Each HT link can be further unganged into two independent 8-bit links. The package has 1132 signal I/O, 341 power, and 471 ground pins. Package size constrained the HT interface to 64 lanes total, one x16 and one x8 link from node 0, two x16 links and one x8 link from node 1. One x16 link on node 0 is not connected, the remaining links connect the nodes in the package. Each link can be used for I/O, e.g. connecting a GPU through a HT-PCI bridge, or for cache coherent inter-socket traffic using an AMD proprietary protocol, with flexible routing permitting various network topologies on 2P and 4P systems. 8P systems were not considered citing insufficient demand.
  
 
[[File:G34 Opteron MP topologies.svg|800px]]
 
[[File:G34 Opteron MP topologies.svg|800px]]
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=== Features ===
 
=== Features ===
* Lidded [[land grid array]] package, 60.0 mm × 42.5 mm
+
* 1944-land lidded [[land grid array]] package, 42.5 × 60.0 mm, 40 × 57 land array, 1.0 mm pitch, organic substrate, [[controlled collapse chip connection|C4]] ([[flip chip]]) die attachment
** 1944 contacts in a 57 × 40 grid with 1.0 mm pitch
 
** Organic substrate, [[controlled collapse chip connection|C4]] [[flip chip]] die attachment
 
  
* 4 × 64/72 bit DDR3 SDRAM interface up to 933 MHz, PC3-14900 (DDR3-1866), 29.87 GB/s total raw bandwidth
+
* 4 × 64/72 bit DDR3 SDRAM interface up to 933 MHz, PC3-14900 (DDR3-1866), 29.9 GB/s
** Up to 12 {{abbr|SR}}/{{abbr|DR}}/{{abbr|4R}} {{abbr|RDIMM}}s, 12 SR/DR {{abbr|LRDIMM}}s (Fam. 15h), or 8 SR/DR {{abbr|UDIMM}}s
+
** Up to 12 SR/DR/QR RDIMMs, 12 SR/DR LRDIMMs (Fam. 15h), or 8 SR/DR UDIMMs
 
** JEDEC 1.5V, 1.35V, 1.25V (Fam. 15h)
 
** JEDEC 1.5V, 1.35V, 1.25V (Fam. 15h)
** ECC supported
+
** SEC-DED ECC support
 
** AMD Memory Controller PowerCap (Fam. 15h)
 
** AMD Memory Controller PowerCap (Fam. 15h)
 
** On-line spare feature provides single-rank DRAM redundancy
 
** On-line spare feature provides single-rank DRAM redundancy
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* Managemement Features
 
* Managemement Features
 
** Advanced Platform Management Link (APML)
 
** Advanced Platform Management Link (APML)
** {{abbr|SMBus}} v2.0-compatible interface
+
** SMBus v2.0-compatible interface
 
** Remote-Management Interface (SB-RMI)
 
** Remote-Management Interface (SB-RMI)
  
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</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}
 
== Photos ==
 
<gallery widths=500px heights=400px>
 
File:Socket G34.jpg|Socket G34, open
 
File:AMD Opteron 6282SE on socket (14470254034).jpg|Socket G34 with Opteron 6282SE installed
 
</gallery>
 
  
 
== Package Diagram ==
 
== Package Diagram ==
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== Pin Map ==
 
== Pin Map ==
[[File:Socket G34 pinmap.svg|800px]]
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No data available.
 
 
Socket G34 pinout, top view. This is a preview, click for a larger image and other views.
 
 
 
<!--
 
ALERT_L,BT5,L2_CTLIN_L[1],R11,MA_WE_L,AU30,MC_DATA[32],BG39,RSVD,D1,VDD,AT6,VLDT,C11,VSS,AF7
 
CLKIN_H,A9,L2_CTLOUT_H[0],U9,MB0_CS_L[0],AV33,MC_DATA[33],BG38,RSVD,D39,VDD,AT12,VLDT,BR3,VSS,AF14
 
CLKIN_L,A10,L2_CTLOUT_H[1],U12,MB0_CS_L[1],BA33,MC_DATA[34],BH35,RSVD,D40,VDD,AT13,VLDT,BR4,VSS,AF26
 
CPU_PRESENT_L,BU13,L2_CTLOUT_L[0],U8,MB0_ODT[0],AY34,MC_DATA[35],BH34,RSVD,E15,VDD,AT15,VLDT,BR6,VSS,AF28
 
DBRDY,BT11,L2_CTLOUT_L[1],U11,MB1_CS_L[0],AV32,MC_DATA[36],BF40,RSVD,F13,VDD,AU2,VLDT,BR7,VSS,AG3
 
DBREQ_L,BT12,L3_CADIN_H[0],AK7,MB1_CS_L[1],AY33,MC_DATA[37],BF39,RSVD,F40,VDD,AU8,VLDT,BR9,VSS,AG9
 
HTREF0,BT2,L3_CADIN_H[1],AL9,MB1_ODT[0],AW31,MC_DATA[38],BG36,RSVD,G1,VDD,AU14,VLDT,BR10,VSS,AG13
 
HTREF1,BT3,L3_CADIN_H[2],AM8,MB2_CS_L[0],BD33,MC_DATA[39],BG35,RSVD,G39,VDD,AV4,VLDT,BR12,VSS,AG15
 
L0_CADIN_H[0],D3,L3_CADIN_H[3],AN7,MB2_CS_L[1],BC34,MC_DATA[40],BG33,RSVD,G40,VDD,AV10,VLDT,BR13,VSS,AG27
 
L0_CADIN_H[1],E2,L3_CADIN_H[4],AU9,MB2_ODT[0],BB32,MC_DATA[41],BG32,RSVD,H2,VDD,AV13,VLDT_SENSE,A4,VSS,AH5
 
L0_CADIN_H[2],F1,L3_CADIN_H[5],AV8,MB3_CS_L[0],BD32,MC_DATA[42],BH29,RSVD,H3,VDD,AV15,VSS,A5,VSS,AH11
 
L0_CADIN_H[3],G3,L3_CADIN_H[6],AW7,MB3_CS_L[1],BC33,MC_DATA[43],BH28,RSVD,H5,VDD,AW6,VSS,A8,VSS,AH14
 
L0_CADIN_H[4],L2,L3_CADIN_H[7],AY9,MB3_ODT[0],BB31,MC_DATA[44],BF34,RSVD,H6,VDD,AW12,VSS,A11,VSS,AH26
 
L0_CADIN_H[5],M1,L3_CADIN_H[8],AK10,MB_ADD[0],AP33,MC_DATA[45],BF33,RSVD,H8,VDD,AW14,VSS,A14,VSS,AH28
 
L0_CADIN_H[6],N3,L3_CADIN_H[9],AL12,MB_ADD[1],AG31,MC_DATA[46],BG30,RSVD,H9,VDD,AY2,VSS,A17,VSS,AJ7
 
L0_CADIN_H[7],P2,L3_CADIN_H[10],AM11,MB_ADD[2],AH34,MC_DATA[47],BG29,RSVD,H15,VDD,AY8,VSS,A20,VSS,AJ13
 
L0_CADIN_H[8],D6,L3_CADIN_H[11],AN10,MB_ADD[3],AG32,MC_DATA[48],BG27,RSVD,J40,VDD,AY15,VSS,A23,VSS,AJ15
 
L0_CADIN_H[9],E5,L3_CADIN_H[12],AU12,MB_ADD[4],AF32,MC_DATA[49],BG26,RSVD,K3,VDD,BA4,VSS,A26,VSS,AK3
 
L0_CADIN_H[10],F4,L3_CADIN_H[13],AV11,MB_ADD[5],AF33,MC_DATA[50],BH23,RSVD,K4,VDD,BA10,VSS,A29,VSS,AK9
 
L0_CADIN_H[11],G6,L3_CADIN_H[14],AW10,MB_ADD[6],AE33,MC_DATA[51],BH22,RSVD,K6,VDD,BA14,VSS,A32,VSS,AK14
 
L0_CADIN_H[12],L5,L3_CADIN_H[15],AY12,MB_ADD[7],AD31,MC_DATA[52],BF28,RSVD,K7,VDD,BB6,VSS,A35,VSS,AK26
 
L0_CADIN_H[13],M4,L3_CADIN_L[0],AK8,MB_ADD[8],AE34,MC_DATA[53],BF27,RSVD,K9,VDD,BB12,VSS,A38,VSS,AL5
 
L0_CADIN_H[14],N6,L3_CADIN_L[1],AL10,MB_ADD[9],AC32,MC_DATA[54],BG24,RSVD,K10,VDD,BB13,VSS,B4,VSS,AL11
 
L0_CADIN_H[15],P5,L3_CADIN_L[2],AM9,MB_ADD[10],AT32,MC_DATA[55],BG23,RSVD,K12,VDD,BB15,VSS,B7,VSS,AL15
 
L0_CADIN_L[0],D4,L3_CADIN_L[3],AN8,MB_ADD[11],AD32,MC_DATA[56],BG21,RSVD,K39,VDD,BC2,VSS,B10,VSS,AL27
 
L0_CADIN_L[1],E3,L3_CADIN_L[4],AU10,MB_ADD[12],AC33,MC_DATA[57],BG20,RSVD,K40,VDD,BC8,VSS,B13,VSS,AM7
 
L0_CADIN_L[2],F2,L3_CADIN_L[5],AV9,MB_ADD[13],BA32,MC_DATA[58],BH17,RSVD,L15,VDD,BC14,VSS,B16,VSS,AM14
 
L0_CADIN_L[3],G4,L3_CADIN_L[6],AW8,MB_ADD[14],AA31,MC_DATA[59],BH16,RSVD,M13,VDD,BC16,VSS,B19,VSS,AM26
 
L0_CADIN_L[4],L3,L3_CADIN_L[7],AY10,MB_ADD[15],AA32,MC_DATA[60],BF22,RSVD,T4,VDD,BC18,VSS,B22,VSS,AM28
 
L0_CADIN_L[5],M2,L3_CADIN_L[8],AK11,MB_BANK[0],AT31,MC_DATA[61],BF21,RSVD,T6,VDD,BC20,VSS,B25,VSS,AN3
 
L0_CADIN_L[6],N4,L3_CADIN_L[9],AL13,MB_BANK[1],AR32,MC_DATA[62],BG18,RSVD,T7,VDD,BC22,VSS,B28,VSS,AN9
 
L0_CADIN_L[7],P3,L3_CADIN_L[10],AM12,MB_BANK[2],AB34,MC_DATA[63],BG17,RSVD,T10,VDD,BC24,VSS,B31,VSS,AN13
 
L0_CADIN_L[8],D7,L3_CADIN_L[11],AN11,MB_CAS_L,AW32,MC_DQS_H[0],K19,RSVD,T12,VDD,BD4,VSS,B34,VSS,AN15
 
L0_CADIN_L[9],E6,L3_CADIN_L[12],AU13,MB_CHECK[0],P32,MC_DQS_H[1],K25,RSVD,T13,VDD,BD10,VSS,B37,VSS,AN27
 
L0_CADIN_L[10],F5,L3_CADIN_L[13],AV12,MB_CHECK[1],P33,MC_DQS_H[2],K31,RSVD,AB3,VDD,BD13,VSS,C3,VSS,AP5
 
L0_CADIN_L[11],G7,L3_CADIN_L[14],AW11,MB_CHECK[2],V31,MC_DQS_H[3],K37,RSVD,AB4,VDD,BD15,VSS,C6,VSS,AP11
 
L0_CADIN_L[12],L6,L3_CADIN_L[15],AY13,MB_CHECK[3],V32,MC_DQS_H[4],BF36,RSVD,AB6,VDD,BD17,VSS,C9,VSS,AP14
 
L0_CADIN_L[13],M5,L3_CADOUT_H[0],BP8,MB_CHECK[4],N33,MC_DQS_H[5],BF30,RSVD,AB7,VDD,BD19,VSS,C12,VSS,AP26
 
L0_CADIN_L[14],N7,L3_CADOUT_H[1],BN9,MB_CHECK[5],N34,MC_DQS_H[6],BF24,RSVD,AB9,VDD,BD21,VSS,C15,VSS,AP28
 
L0_CADIN_L[15],P6,L3_CADOUT_H[2],BM10,MB_CHECK[6],U32,MC_DQS_H[7],BF18,RSVD,AB10,VDD,BD23,VSS,C18,VSS,AR7
 
L0_CADOUT_H[0],AH4,L3_CADOUT_H[3],BL8,MB_CHECK[7],U33,MC_DQS_H[8],T37,RSVD,AB12,VDD,BD25,VSS,C21,VSS,AR13
 
L0_CADOUT_H[1],AG2,L3_CADOUT_H[4],BG9,MB_CKE[0],Y32,MC_DQS_H[9],L17,RSVD,AB13,VDD,BE6,VSS,C24,VSS,AR15
 
L0_CADOUT_H[2],AF3,L3_CADOUT_H[5],BF10,MB_CKE[1],Y33,MC_DQS_H[10],L23,RSVD,AD1,VDD,BE12,VSS,C27,VSS,AR27
 
L0_CADOUT_H[3],AE4,L3_CADOUT_H[6],BE8,MB_CLK_H[0],AM33,MC_DQS_H[11],L29,RSVD,AD2,VDD,BE14,VSS,C30,VSS,AT3
 
L0_CADOUT_H[4],AA2,L3_CADOUT_H[7],BD9,MB_CLK_H[1],AN32,MC_DQS_H[12],L35,RSVD,AD4,VDD,BE16,VSS,C33,VSS,AT9
 
L0_CADOUT_H[5],Y3,L3_CADOUT_H[8],BP11,MB_CLK_H[2],AL34,MC_DQS_H[13],BH38,RSVD,AD5,VDD,BE18,VSS,C36,VSS,AT14
 
L0_CADOUT_H[6],W4,L3_CADOUT_H[9],BN12,MB_CLK_H[3],AK32,MC_DQS_H[14],BH32,RSVD,AD7,VDD,BE20,VSS,C39,VSS,AT26
 
L0_CADOUT_H[7],V2,L3_CADOUT_H[10],BM13,MB_CLK_H[4],AJ33,MC_DQS_H[15],BH26,RSVD,AD8,VDD,BE22,VSS,D5,VSS,AU5
 
L0_CADOUT_H[8],AH7,L3_CADOUT_H[11],BL11,MB_CLK_L[0],AM32,MC_DQS_H[16],BH20,RSVD,AD10,VDD,BE24,VSS,D11,VSS,AU11
 
L0_CADOUT_H[9],AG5,L3_CADOUT_H[12],BG12,MB_CLK_L[1],AN31,MC_DQS_H[17],R34,RSVD,AD11,VDD,BE26,VSS,D17,VSS,AU15
 
L0_CADOUT_H[10],AF6,L3_CADOUT_H[13],BF13,MB_CLK_L[2],AL33,MC_DQS_L[0],K18,RSVD,AH30,VDD,BF2,VSS,D20,VSS,AU27
 
L0_CADOUT_H[11],AE7,L3_CADOUT_H[14],BE11,MB_CLK_L[3],AK31,MC_DQS_L[1],K24,RSVD,AH33,VDD,BF8,VSS,D23,VSS,AV7
 
L0_CADOUT_H[12],AA5,L3_CADOUT_H[15],BD12,MB_CLK_L[4],AJ32,MC_DQS_L[2],K30,RSVD,AH36,VDD,BG4,VSS,D26,VSS,AV14
 
L0_CADOUT_H[13],Y6,L3_CADOUT_L[0],BP7,MB_DATA[0],J16,MC_DQS_L[3],K36,RSVD,AH39,VDD,BG10,VSS,D29,VSS,AV26
 
L0_CADOUT_H[14],W7,L3_CADOUT_L[1],BN8,MB_DATA[1],J17,MC_DQS_L[4],BF37,RSVD,AJ2,VDD,BH6,VSS,D32,VSS,AV28
 
L0_CADOUT_H[15],V5,L3_CADOUT_L[2],BM9,MB_DATA[2],H20,MC_DQS_L[5],BF31,RSVD,AJ3,VDD,BH12,VSS,D35,VSS,AW3
 
L0_CADOUT_L[0],AH3,L3_CADOUT_L[3],BL7,MB_DATA[3],H21,MC_DQS_L[6],BF25,RSVD,AJ5,VDD,BJ2,VSS,D38,VSS,AW9
 
L0_CADOUT_L[1],AG1,L3_CADOUT_L[4],BG8,MB_DATA[4],G15,MC_DQS_L[7],BF19,RSVD,AJ6,VDD,BJ8,VSS,E1,VSS,AW13
 
L0_CADOUT_L[2],AF2,L3_CADOUT_L[5],BF9,MB_DATA[5],G16,MC_DQS_L[8],T36,RSVD,AJ8,VDD,BK4,VSS,E7,VSS,AW15
 
L0_CADOUT_L[3],AE3,L3_CADOUT_L[6],BE7,MB_DATA[6],J19,MC_DQS_L[9],L18,RSVD,AJ9,VDD,BK10,VSS,E13,VSS,AW27
 
L0_CADOUT_L[4],AA1,L3_CADOUT_L[7],BD8,MB_DATA[7],J20,MC_DQS_L[10],L24,RSVD,AT1,VDD,BL6,VSS,E16,VSS,AY5
 
L0_CADOUT_L[5],Y2,L3_CADOUT_L[8],BP10,MB_DATA[8],J22,MC_DQS_L[11],L30,RSVD,AT2,VDD,BL12,VSS,E19,VSS,AY11
 
L0_CADOUT_L[6],W3,L3_CADOUT_L[9],BN11,MB_DATA[9],J23,MC_DQS_L[12],L36,RSVD,AT4,VDD,BM2,VSS,E22,VSS,AY14
 
L0_CADOUT_L[7],V1,L3_CADOUT_L[10],BM12,MB_DATA[10],H26,MC_DQS_L[13],BH37,RSVD,AT5,VDD,BM8,VSS,E25,VSS,AY26
 
L0_CADOUT_L[8],AH6,L3_CADOUT_L[11],BL10,MB_DATA[11],H27,MC_DQS_L[14],BH31,RSVD,AT7,VDD,BM14,VSS,E28,VSS,AY28
 
L0_CADOUT_L[9],AG4,L3_CADOUT_L[12],BG11,MB_DATA[12],G21,MC_DQS_L[15],BH25,RSVD,AT8,VDD,BN4,VSS,E31,VSS,BA7
 
L0_CADOUT_L[10],AF5,L3_CADOUT_L[13],BF12,MB_DATA[13],G22,MC_DQS_L[16],BH19,RSVD,AT10,VDD,BN10,VSS,E34,VSS,BA13
 
L0_CADOUT_L[11],AE6,L3_CADOUT_L[14],BE10,MB_DATA[14],J25,MC_DQS_L[17],R35,RSVD,AT11,VDD,BP6,VSS,E37,VSS,BA15
 
L0_CADOUT_L[12],AA4,L3_CADOUT_L[15],BD11,MB_DATA[15],J26,MC_ERR_L,AB36,RSVD,BB2,VDD,BP12,VSS,E40,VSS,BA27
 
L0_CADOUT_L[13],Y5,L3_CLKIN_H[0],AR8,MB_DATA[16],J28,MC_EVENT_L,AP37,RSVD,BB4,VDDA,BF15,VSS,F3,VSS,BB1
 
L0_CADOUT_L[14],W6,L3_CLKIN_H[1],AR11,MB_DATA[17],J29,MC_PAR,AR36,RSVD,BB5,VDDA,BF16,VSS,F9,VSS,BB3
 
L0_CADOUT_L[15],V4,L3_CLKIN_L[0],AR9,MB_DATA[18],H32,MC_RAS_L,AU37,RSVD,BB8,VDDA,BG14,VSS,F15,VSS,BB7
 
L0_CLKIN_H[0],J1,L3_CLKIN_L[1],AR12,MB_DATA[19],H33,MC_RESET_L,W36,RSVD,BE13,VDDA,BG15,VSS,F18,VSS,BB9
 
L0_CLKIN_H[1],J4,L3_CLKOUT_H[0],BJ10,MB_DATA[20],G27,MC_WE_L,AU36,RSVD,BE28,VDDIO,Y27,VSS,F21,VSS,BB14
 
L0_CLKIN_L[0],J2,L3_CLKOUT_H[1],BJ13,MB_DATA[21],G28,MD0_CS_L[0],AV39,RSVD,BE29,VDDIO,Y31,VSS,F24,VSS,BB26
 
L0_CLKIN_L[1],J5,L3_CLKOUT_L[0],BJ9,MB_DATA[22],J31,MD0_CS_L[1],BA39,RSVD,BE31,VDDIO,Y34,VSS,F27,VSS,BC5
 
L0_CLKOUT_H[0],AC3,L3_CLKOUT_L[1],BJ12,MB_DATA[23],J32,MD0_ODT[0],AY40,RSVD,BE32,VDDIO,Y37,VSS,F30,VSS,BC11
 
L0_CLKOUT_H[1],AC6,L3_CTLIN_H[0],BA8,MB_DATA[24],J34,MD1_CS_L[0],AV38,RSVD,BE34,VDDIO,AA26,VSS,F33,VSS,BC15
 
L0_CLKOUT_L[0],AC2,L3_CTLIN_H[1],BA11,MB_DATA[25],J35,MD1_CS_L[1],AY39,RSVD,BE35,VDDIO,AA30,VSS,F36,VSS,BC17
 
L0_CLKOUT_L[1],AC5,L3_CTLIN_L[0],BA9,MB_DATA[26],H38,MD1_ODT[0],AW37,RSVD,BE37,VDDIO,AA33,VSS,F39,VSS,BC19
 
L0_CTLIN_H[0],R1,L3_CTLIN_L[1],BA12,MB_DATA[27],H39,MD2_CS_L[0],BD39,RSVD,BH1,VDDIO,AA36,VSS,G5,VSS,BC21
 
L0_CTLIN_H[1],R4,L3_CTLOUT_H[0],BC10,MB_DATA[28],G33,MD2_CS_L[1],BC40,RSVD,BH2,VDDIO,AA39,VSS,G11,VSS,BC23
 
L0_CTLIN_L[0],R2,L3_CTLOUT_H[1],BC13,MB_DATA[29],G34,MD2_ODT[0],BB38,RSVD,BH4,VDDIO,AB27,VSS,G17,VSS,BC25
 
L0_CTLIN_L[1],R5,L3_CTLOUT_L[0],BC9,MB_DATA[30],J37,MD3_CS_L[0],BD38,RSVD,BH5,VDDIO,AB29,VSS,G20,VSS,BC27
 
L0_CTLOUT_H[0],U3,L3_CTLOUT_L[1],BC12,MB_DATA[31],J38,MD3_CS_L[1],BC39,RSVD,BH7,VDDIO,AB32,VSS,G23,VSS,BD7
 
L0_CTLOUT_H[1],U6,LDTSTOP_L,B5,MB_DATA[32],BK39,MD3_ODT[0],BB37,RSVD,BH8,VDDIO,AB35,VSS,G26,VSS,BD14
 
L0_CTLOUT_L[0],U2,MA0_CS_L[0],AV30,MB_DATA[33],BK38,MD_ADD[0],AP39,RSVD,BH10,VDDIO,AB38,VSS,G29,VSS,BD16
 
L0_CTLOUT_L[1],U5,MA0_CS_L[1],BA30,MB_DATA[34],BL35,MD_ADD[1],AG37,RSVD,BH11,VDDIO,AC26,VSS,G32,VSS,BD18
 
L1_CADIN_H[0],AK1,MA0_ODT[0],AY31,MB_DATA[35],BL34,MD_ADD[2],AH40,RSVD,BH13,VDDIO,AC28,VSS,G35,VSS,BD20
 
L1_CADIN_H[1],AL3,MA1_CS_L[0],AV29,MB_DATA[36],BJ40,MD_ADD[3],AG38,RSVD,BH14,VDDIO,AC31,VSS,G38,VSS,BD22
 
L1_CADIN_H[2],AM2,MA1_CS_L[1],AY30,MB_DATA[37],BJ39,MD_ADD[4],AF38,RSVD,BJ1,VDDIO,AC34,VSS,H1,VSS,BD24
 
L1_CADIN_H[3],AN1,MA1_ODT[0],AW28,MB_DATA[38],BK36,MD_ADD[5],AF39,RSVD,BJ15,VDDIO,AC37,VSS,H7,VSS,BD26
 
L1_CADIN_H[4],AU3,MA2_CS_L[0],BD30,MB_DATA[39],BK35,MD_ADD[6],AE39,RSVD,BJ16,VDDIO,AD27,VSS,H13,VSS,BD28
 
L1_CADIN_H[5],AV2,MA2_CS_L[1],BC31,MB_DATA[40],BK33,MD_ADD[7],AD37,RSVD,BL13,VDDIO,AD30,VSS,H16,VSS,BE3
 
L1_CADIN_H[6],AW1,MA2_ODT[0],BB29,MB_DATA[41],BK32,MD_ADD[8],AE40,RSVD,BL14,VDDIO,AD33,VSS,H19,VSS,BE9
 
L1_CADIN_H[7],AY3,MA3_CS_L[0],BD29,MB_DATA[42],BL29,MD_ADD[9],AC38,RSVD,BL40,VDDIO,AD36,VSS,H22,VSS,BE15
 
L1_CADIN_H[8],AK4,MA3_CS_L[1],BC30,MB_DATA[43],BL28,MD_ADD[10],AT38,RSVD,BM1,VDDIO,AD39,VSS,H25,VSS,BE17
 
L1_CADIN_H[9],AL6,MA3_ODT[0],BB28,MB_DATA[44],BJ34,MD_ADD[11],AD38,RSVD,BM15,VDDIO,AE26,VSS,H28,VSS,BE19
 
L1_CADIN_H[10],AM5,MA_ADD[0],AP30,MB_DATA[45],BJ33,MD_ADD[12],AC39,RSVD,BM16,VDDIO,AE28,VSS,H31,VSS,BE21
 
L1_CADIN_H[11],AN4,MA_ADD[1],AG28,MB_DATA[46],BK30,MD_ADD[13],BA38,RSVD,BN14,VDDIO,AE29,VSS,H34,VSS,BE23
 
L1_CADIN_H[12],AU6,MA_ADD[2],AH31,MB_DATA[47],BK29,MD_ADD[14],AA37,RSVD,BN15,VDDIO,AE32,VSS,H37,VSS,BE25
 
L1_CADIN_H[13],AV5,MA_ADD[3],AG29,MB_DATA[48],BK27,MD_ADD[15],AA38,RSVD,BP13,VDDIO,AE35,VSS,H40,VSS,BE27
 
L1_CADIN_H[14],AW4,MA_ADD[4],AF29,MB_DATA[49],BK26,MD_BANK[0],AT37,RSVD,BP14,VDDIO,AE38,VSS,J3,VSS,BE30
 
L1_CADIN_H[15],AY6,MA_ADD[5],AF30,MB_DATA[50],BL23,MD_BANK[1],AR38,RSVD,BP40,VDDIO,AF27,VSS,J9,VSS,BE33
 
L1_CADIN_L[0],AK2,MA_ADD[6],AE30,MB_DATA[51],BL22,MD_BANK[2],AB40,RSVD,BU14,VDDIO,AF31,VSS,J15,VSS,BE36
 
L1_CADIN_L[1],AL4,MA_ADD[7],AD28,MB_DATA[52],BJ28,MD_CAS_L,AW38,SA[0],BK2,VDDIO,AF34,VSS,J18,VSS,BE39
 
L1_CADIN_L[2],AM3,MA_ADD[8],AE31,MB_DATA[53],BJ27,MD_CHECK[0],P38,SA[1],BK3,VDDIO,AF37,VSS,J21,VSS,BF5
 
L1_CADIN_L[3],AN2,MA_ADD[9],AC29,MB_DATA[54],BK24,MD_CHECK[1],P39,SA[2],BK5,VDDIO,AG26,VSS,J24,VSS,BF11
 
L1_CADIN_L[4],AU4,MA_ADD[10],AT29,MB_DATA[55],BK23,MD_CHECK[2],V37,SIC,BU4,VDDIO,AG30,VSS,J27,VSS,BF14
 
L1_CADIN_L[5],AV3,MA_ADD[11],AD29,MB_DATA[56],BK21,MD_CHECK[3],V38,SID,BU5,VDDIO,AG33,VSS,J30,VSS,BF17
 
L1_CADIN_L[6],AW2,MA_ADD[12],AC30,MB_DATA[57],BK20,MD_CHECK[4],N39,SVC,A6,VDDIO,AG36,VSS,J33,VSS,BF20
 
L1_CADIN_L[7],AY4,MA_ADD[13],BA29,MB_DATA[58],BL17,MD_CHECK[5],N40,SVD,A7,VDDIO,AG39,VSS,J36,VSS,BF23
 
L1_CADIN_L[8],AK5,MA_ADD[14],AA28,MB_DATA[59],BL16,MD_CHECK[6],U38,TCK,BT9,VDDIO,AH29,VSS,J39,VSS,BF26
 
L1_CADIN_L[9],AL7,MA_ADD[15],AA29,MB_DATA[60],BJ22,MD_CHECK[7],U39,TDI,BT8,VDDIO,AH32,VSS,K5,VSS,BF29
 
L1_CADIN_L[10],AM6,MA_BANK[0],AT28,MB_DATA[61],BJ21,MD_CKE[0],Y38,TDO,BU8,VDDIO,AH35,VSS,K11,VSS,BF32
 
L1_CADIN_L[11],AN5,MA_BANK[1],AR29,MB_DATA[62],BK18,MD_CKE[1],Y39,TEST2,BK8,VDDIO,AH38,VSS,K17,VSS,BF35
 
L1_CADIN_L[12],AU7,MA_BANK[2],AB31,MB_DATA[63],BK17,MD_CLK_H[0],AM39,TEST3,BK9,VDDIO,AJ26,VSS,K20,VSS,BF38
 
L1_CADIN_L[13],AV6,MA_CAS_L,AW29,MB_DQS_H[0],G19,MD_CLK_H[1],AN38,TEST4[0],J13,VDDIO,AJ31,VSS,K23,VSS,BG7
 
L1_CADIN_L[14],AW5,MA_CHECK[0],P29,MB_DQS_H[1],G25,MD_CLK_H[2],AL40,TEST4[1],BK14,VDDIO,AJ34,VSS,K26,VSS,BG13
 
L1_CADIN_L[15],AY7,MA_CHECK[1],P30,MB_DQS_H[2],G31,MD_CLK_H[3],AK38,TEST5[0],K13,VDDIO,AJ37,VSS,K29,VSS,BG16
 
L1_CADOUT_H[0],BP2,MA_CHECK[2],V28,MB_DQS_H[3],G37,MD_CLK_H[4],AJ39,TEST5[1],BK15,VDDIO,AK27,VSS,K32,VSS,BG19
 
L1_CADOUT_H[1],BN3,MA_CHECK[3],V29,MB_DQS_H[4],BJ36,MD_CLK_L[0],AM38,TEST6,BK6,VDDIO,AK30,VSS,K35,VSS,BG22
 
L1_CADOUT_H[2],BM4,MA_CHECK[4],N30,MB_DQS_H[5],BJ30,MD_CLK_L[1],AN37,TEST7,BK12,VDDIO,AK33,VSS,K38,VSS,BG25
 
L1_CADOUT_H[3],BL2,MA_CHECK[5],N31,MB_DQS_H[6],BJ24,MD_CLK_L[2],AL39,TEST8,BK11,VDDIO,AK36,VSS,L7,VSS,BG28
 
L1_CADOUT_H[4],BG3,MA_CHECK[6],U29,MB_DQS_H[7],BJ18,MD_CLK_L[3],AK37,TEST9,BB10,VDDIO,AK39,VSS,L13,VSS,BG31
 
L1_CADOUT_H[5],BF4,MA_CHECK[7],U30,MB_DQS_H[8],T34,MD_CLK_L[4],AJ38,TEST10,BB11,VDDIO,AL26,VSS,L16,VSS,BG34
 
L1_CADOUT_H[6],BE2,MA_CKE[0],Y29,MB_DQS_H[9],H17,MD_DATA[0],C16,TEST11,L14,VDDIO,AL28,VSS,L19,VSS,BG37
 
L1_CADOUT_H[7],BD3,MA_CKE[1],Y30,MB_DQS_H[10],H23,MD_DATA[1],C17,TEST14,E14,VDDIO,AL29,VSS,L22,VSS,BH3
 
L1_CADOUT_H[8],BP5,MA_CLK_H[0],AM30,MB_DQS_H[11],H29,MD_DATA[2],B20,TEST15,F14,VDDIO,AL32,VSS,L25,VSS,BH9
 
L1_CADOUT_H[9],BN6,MA_CLK_H[1],AN29,MB_DQS_H[12],H35,MD_DATA[3],B21,TEST16,H14,VDDIO,AL35,VSS,L28,VSS,BH15
 
L1_CADOUT_H[10],BM7,MA_CLK_H[2],AL31,MB_DQS_H[13],BL38,MD_DATA[4],A15,TEST17,J14,VDDIO,AL38,VSS,L31,VSS,BH18
 
L1_CADOUT_H[11],BL5,MA_CLK_H[3],AK29,MB_DQS_H[14],BL32,MD_DATA[5],A16,TEST18,AP13,VDDIO,AM27,VSS,L34,VSS,BH21
 
L1_CADOUT_H[12],BG6,MA_CLK_H[4],AJ30,MB_DQS_H[15],BL26,MD_DATA[6],C19,TEST19,AP12,VDDIO,AM31,VSS,L37,VSS,BH24
 
L1_CADOUT_H[13],BF7,MA_CLK_L[0],AM29,MB_DQS_H[16],BL20,MD_DATA[7],C20,TEST20,AP10,VDDIO,AM34,VSS,M3,VSS,BH27
 
L1_CADOUT_H[14],BE5,MA_CLK_L[1],AN28,MB_DQS_H[17],R31,MD_DATA[8],C22,TEST21,AP3,VDDIO,AM37,VSS,M9,VSS,BH30
 
L1_CADOUT_H[15],BD6,MA_CLK_L[2],AL30,MB_DQS_L[0],G18,MD_DATA[9],C23,TEST22,AP4,VDDIO,AN26,VSS,M15,VSS,BH33
 
L1_CADOUT_L[0],BP1,MA_CLK_L[3],AK28,MB_DQS_L[1],G24,MD_DATA[10],B26,TEST23,AP6,VDDIO,AN30,VSS,M18,VSS,BH36
 
L1_CADOUT_L[1],BN2,MA_CLK_L[4],AJ29,MB_DQS_L[2],G30,MD_DATA[11],B27,TEST24,AP9,VDDIO,AN33,VSS,M21,VSS,BH39
 
L1_CADOUT_L[2],BM3,MA_DATA[0],F16,MB_DQS_L[3],G36,MD_DATA[12],A21,TEST25_H,A12,VDDIO,AN36,VSS,M24,VSS,BJ5
 
L1_CADOUT_L[3],BL1,MA_DATA[1],F17,MB_DQS_L[4],BJ37,MD_DATA[13],A22,TEST25_L,A13,VDDIO,AN39,VSS,M27,VSS,BJ11
 
L1_CADOUT_L[4],BG2,MA_DATA[2],E20,MB_DQS_L[5],BJ31,MD_DATA[14],C25,TEST27,AP7,VDDIO,AP27,VSS,M30,VSS,BJ14
 
L1_CADOUT_L[5],BF3,MA_DATA[3],E21,MB_DQS_L[6],BJ25,MD_DATA[15],C26,TEST28_H[0],H11,VDDIO,AP29,VSS,M33,VSS,BJ17
 
L1_CADOUT_L[6],BE1,MA_DATA[4],D15,MB_DQS_L[7],BJ19,MD_DATA[16],C28,TEST28_H[1],AJ11,VDDIO,AP32,VSS,M36,VSS,BJ20
 
L1_CADOUT_L[7],BD2,MA_DATA[5],D16,MB_DQS_L[8],T33,MD_DATA[17],C29,TEST28_L[0],H12,VDDIO,AP35,VSS,M39,VSS,BJ23
 
L1_CADOUT_L[8],BP4,MA_DATA[6],F19,MB_DQS_L[9],H18,MD_DATA[18],B32,TEST28_L[1],AJ12,VDDIO,AP38,VSS,N5,VSS,BJ26
 
L1_CADOUT_L[9],BN5,MA_DATA[7],F20,MB_DQS_L[10],H24,MD_DATA[19],B33,TEST36,M14,VDDIO,AR26,VSS,N11,VSS,BJ29
 
L1_CADOUT_L[10],BM6,MA_DATA[8],F22,MB_DQS_L[11],H30,MD_DATA[20],A27,THERMTRIP_L,BT6,VDDIO,AR28,VSS,N15,VSS,BJ32
 
L1_CADOUT_L[11],BL4,MA_DATA[9],F23,MB_DQS_L[12],H36,MD_DATA[21],A28,TMS,BU10,VDDIO,AR31,VSS,N17,VSS,BJ35
 
L1_CADOUT_L[12],BG5,MA_DATA[10],E26,MB_DQS_L[13],BL37,MD_DATA[22],C31,TRST_L,BU11,VDDIO,AR34,VSS,N19,VSS,BJ38
 
L1_CADOUT_L[13],BF6,MA_DATA[11],E27,MB_DQS_L[14],BL31,MD_DATA[23],C32,VDD,D2,VDDIO,AR37,VSS,N21,VSS,BK1
 
L1_CADOUT_L[14],BE4,MA_DATA[12],D21,MB_DQS_L[15],BL25,MD_DATA[24],C34,VDD,D8,VDDIO,AT27,VSS,N23,VSS,BK7
 
L1_CADOUT_L[15],BD5,MA_DATA[13],D22,MB_DQS_L[16],BL19,MD_DATA[25],C35,VDD,D14,VDDIO,AT30,VSS,N25,VSS,BK13
 
L1_CLKIN_H[0],AR2,MA_DATA[14],F25,MB_DQS_L[17],R32,MD_DATA[26],B38,VDD,E4,VDDIO,AT33,VSS,N27,VSS,BK16
 
L1_CLKIN_H[1],AR5,MA_DATA[15],F26,MB_ERR_L,AB33,MD_DATA[27],B39,VDD,E10,VDDIO,AT36,VSS,N29,VSS,BK19
 
L1_CLKIN_L[0],AR3,MA_DATA[16],F28,MB_EVENT_L,AP34,MD_DATA[28],A33,VDD,F6,VDDIO,AT39,VSS,N32,VSS,BK22
 
L1_CLKIN_L[1],AR6,MA_DATA[17],F29,MB_PAR,AR33,MD_DATA[29],A34,VDD,F12,VDDIO,AU26,VSS,N35,VSS,BK25
 
L1_CLKOUT_H[0],BJ4,MA_DATA[18],E32,MB_RAS_L,AU34,MD_DATA[30],C37,VDD,G2,VDDIO,AU28,VSS,N38,VSS,BK28
 
L1_CLKOUT_H[1],BJ7,MA_DATA[19],E33,MB_RESET_L,W33,MD_DATA[31],C38,VDD,G8,VDDIO,AU29,VSS,P7,VSS,BK31
 
L1_CLKOUT_L[0],BJ3,MA_DATA[20],D27,MB_WE_L,AU33,MD_DATA[32],BT39,VDD,G14,VDDIO,AU32,VSS,P14,VSS,BK34
 
L1_CLKOUT_L[1],BJ6,MA_DATA[21],D28,MC0_CS_L[0],AV36,MD_DATA[33],BT38,VDD,H4,VDDIO,AU35,VSS,P16,VSS,BK37
 
L1_CTLIN_H[0],BA2,MA_DATA[22],F31,MC0_CS_L[1],BA36,MD_DATA[34],BU35,VDD,H10,VDDIO,AU38,VSS,P18,VSS,BK40
 
L1_CTLIN_H[1],BA5,MA_DATA[23],F32,MC0_ODT[0],AY37,MD_DATA[35],BU34,VDD,J6,VDDIO,AV27,VSS,P20,VSS,BL3
 
L1_CTLIN_L[0],BA3,MA_DATA[24],F34,MC1_CS_L[0],AV35,MD_DATA[36],BR40,VDD,J12,VDDIO,AV31,VSS,P22,VSS,BL9
 
L1_CTLIN_L[1],BA6,MA_DATA[25],F35,MC1_CS_L[1],AY36,MD_DATA[37],BR39,VDD,K2,VDDIO,AV34,VSS,P24,VSS,BL15
 
L1_CTLOUT_H[0],BC4,MA_DATA[26],E38,MC1_ODT[0],AW34,MD_DATA[38],BT36,VDD,K8,VDDIO,AV37,VSS,P26,VSS,BL18
 
L1_CTLOUT_H[1],BC7,MA_DATA[27],E39,MC2_CS_L[0],BD36,MD_DATA[39],BT35,VDD,K14,VDDIO,AW26,VSS,P28,VSS,BL21
 
L1_CTLOUT_L[0],BC3,MA_DATA[28],D33,MC2_CS_L[1],BC37,MD_DATA[40],BT33,VDD,L4,VDDIO,AW30,VSS,P31,VSS,BL24
 
L1_CTLOUT_L[1],BC6,MA_DATA[29],D34,MC2_ODT[0],BB35,MD_DATA[41],BT32,VDD,L10,VDDIO,AW33,VSS,P34,VSS,BL27
 
L2_CADIN_H[0],D9,MA_DATA[30],F37,MC3_CS_L[0],BD35,MD_DATA[42],BU29,VDD,M6,VDDIO,AW36,VSS,P37,VSS,BL30
 
L2_CADIN_H[1],E8,MA_DATA[31],F38,MC3_CS_L[1],BC36,MD_DATA[43],BU28,VDD,M12,VDDIO,AW39,VSS,R3,VSS,BL33
 
L2_CADIN_H[2],F7,MA_DATA[32],BN39,MC3_ODT[0],BB34,MD_DATA[44],BR34,VDD,N2,VDDIO,AY27,VSS,R9,VSS,BL36
 
L2_CADIN_H[3],G9,MA_DATA[33],BN38,MC_ADD[0],AP36,MD_DATA[45],BR33,VDD,N8,VDDIO,AY29,VSS,R13,VSS,BL39
 
L2_CADIN_H[4],L8,MA_DATA[34],BP35,MC_ADD[1],AG34,MD_DATA[46],BT30,VDD,P4,VDDIO,AY32,VSS,R15,VSS,BM5
 
L2_CADIN_H[5],M7,MA_DATA[35],BP34,MC_ADD[2],AH37,MD_DATA[47],BT29,VDD,P10,VDDIO,AY35,VSS,R17,VSS,BM11
 
L2_CADIN_H[6],N9,MA_DATA[36],BM40,MC_ADD[3],AG35,MD_DATA[48],BT27,VDD,P13,VDDIO,AY38,VSS,R19,VSS,BM17
 
L2_CADIN_H[7],P8,MA_DATA[37],BM39,MC_ADD[4],AF35,MD_DATA[49],BT26,VDD,R6,VDDIO,BA26,VSS,R21,VSS,BM20
 
L2_CADIN_H[8],D12,MA_DATA[38],BN36,MC_ADD[5],AF36,MD_DATA[50],BU23,VDD,R12,VDDIO,BA28,VSS,R23,VSS,BM23
 
L2_CADIN_H[9],E11,MA_DATA[39],BN35,MC_ADD[6],AE36,MD_DATA[51],BU22,VDD,T2,VDDIO,BA31,VSS,R25,VSS,BM26
 
L2_CADIN_H[10],F10,MA_DATA[40],BN33,MC_ADD[7],AD34,MD_DATA[52],BR28,VDD,T8,VDDIO,BA34,VSS,R27,VSS,BM29
 
L2_CADIN_H[11],G12,MA_DATA[41],BN32,MC_ADD[8],AE37,MD_DATA[53],BR27,VDD,T15,VDDIO,BA37,VSS,R30,VSS,BM32
 
L2_CADIN_H[12],L11,MA_DATA[42],BP29,MC_ADD[9],AC35,MD_DATA[54],BT24,VDD,U4,VDDIO,BB27,VSS,R33,VSS,BM35
 
L2_CADIN_H[13],M10,MA_DATA[43],BP28,MC_ADD[10],AT35,MD_DATA[55],BT23,VDD,U10,VDDIO,BB30,VSS,R36,VSS,BM38
 
L2_CADIN_H[14],N12,MA_DATA[44],BM34,MC_ADD[11],AD35,MD_DATA[56],BT21,VDD,U14,VDDIO,BB33,VSS,R39,VSS,BN1
 
L2_CADIN_H[15],P11,MA_DATA[45],BM33,MC_ADD[12],AC36,MD_DATA[57],BT20,VDD,V6,VDDIO,BB36,VSS,T3,VSS,BN7
 
L2_CADIN_L[0],D10,MA_DATA[46],BN30,MC_ADD[13],BA35,MD_DATA[58],BU17,VDD,V12,VDDIO,BB39,VSS,T5,VSS,BN13
 
L2_CADIN_L[1],E9,MA_DATA[47],BN29,MC_ADD[14],AA34,MD_DATA[59],BU16,VDD,V13,VDDIO,BC26,VSS,T9,VSS,BN16
 
L2_CADIN_L[2],F8,MA_DATA[48],BN27,MC_ADD[15],AA35,MD_DATA[60],BR22,VDD,V15,VDDIO,BC28,VSS,T11,VSS,BN19
 
L2_CADIN_L[3],G10,MA_DATA[49],BN26,MC_BANK[0],AT34,MD_DATA[61],BR21,VDD,W2,VDDIO,BC29,VSS,T14,VSS,BN22
 
L2_CADIN_L[4],L9,MA_DATA[50],BP23,MC_BANK[1],AR35,MD_DATA[62],BT18,VDD,W8,VDDIO,BC32,VSS,T26,VSS,BN25
 
L2_CADIN_L[5],M8,MA_DATA[51],BP22,MC_BANK[2],AB37,MD_DATA[63],BT17,VDD,W14,VDDIO,BC35,VSS,T28,VSS,BN28
 
L2_CADIN_L[6],N10,MA_DATA[52],BM28,MC_CAS_L,AW35,MD_DQS_H[0],A19,VDD,Y4,VDDIO,BC38,VSS,T29,VSS,BN31
 
L2_CADIN_L[7],P9,MA_DATA[53],BM27,MC_CHECK[0],P35,MD_DQS_H[1],A25,VDD,Y10,VDDIO,BD27,VSS,T32,VSS,BN34
 
L2_CADIN_L[8],D13,MA_DATA[54],BN24,MC_CHECK[1],P36,MD_DQS_H[2],A31,VDD,Y13,VDDIO,BD31,VSS,T35,VSS,BN37
 
L2_CADIN_L[9],E12,MA_DATA[55],BN23,MC_CHECK[2],V34,MD_DQS_H[3],A37,VDD,Y15,VDDIO,BD34,VSS,T38,VSS,BN40
 
L2_CADIN_L[10],F11,MA_DATA[56],BN21,MC_CHECK[3],V35,MD_DQS_H[4],BR36,VDD,AA6,VDDIO,BD37,VSS,U7,VSS,BP3
 
L2_CADIN_L[11],G13,MA_DATA[57],BN20,MC_CHECK[4],N36,MD_DQS_H[5],BR30,VDD,AA12,VDDIO_FB_H,AJ28,VSS,U13,VSS,BP9
 
L2_CADIN_L[12],L12,MA_DATA[58],BP17,MC_CHECK[5],N37,MD_DQS_H[6],BR24,VDD,AA14,VDDIO_FB_L,AJ27,VSS,U15,VSS,BP15
 
L2_CADIN_L[13],M11,MA_DATA[59],BP16,MC_CHECK[6],U35,MD_DQS_H[7],BR18,VDD,AB2,VDDNB,N14,VSS,U27,VSS,BP18
 
L2_CADIN_L[14],N13,MA_DATA[60],BM22,MC_CHECK[7],U36,MD_DQS_H[8],T40,VDD,AB8,VDDNB,N16,VSS,U31,VSS,BP21
 
L2_CADIN_L[15],P12,MA_DATA[61],BM21,MC_CKE[0],Y35,MD_DQS_H[9],B17,VDD,AB15,VDDNB,N18,VSS,U34,VSS,BP24
 
L2_CADOUT_H[0],AH10,MA_DATA[62],BN18,MC_CKE[1],Y36,MD_DQS_H[10],B23,VDD,AC4,VDDNB,N20,VSS,U37,VSS,BP27
 
L2_CADOUT_H[1],AG8,MA_DATA[63],BN17,MC_CLK_H[0],AM36,MD_DQS_H[11],B29,VDD,AC10,VDDNB,N22,VSS,V3,VSS,BP30
 
L2_CADOUT_H[2],AF9,MA_DQS_H[0],D19,MC_CLK_H[1],AN35,MD_DQS_H[12],B35,VDD,AC14,VDDNB,N24,VSS,V9,VSS,BP33
 
L2_CADOUT_H[3],AE10,MA_DQS_H[1],D25,MC_CLK_H[2],AL37,MD_DQS_H[13],BU38,VDD,AD6,VDDNB,N26,VSS,V14,VSS,BP36
 
L2_CADOUT_H[4],AA8,MA_DQS_H[2],D31,MC_CLK_H[3],AK35,MD_DQS_H[14],BU32,VDD,AD12,VDDNB,N28,VSS,V26,VSS,BP39
 
L2_CADOUT_H[5],Y9,MA_DQS_H[3],D37,MC_CLK_H[4],AJ36,MD_DQS_H[15],BU26,VDD,AD13,VDDNB,P15,VSS,V30,VSS,BR2
 
L2_CADOUT_H[6],W10,MA_DQS_H[4],BM36,MC_CLK_L[0],AM35,MD_DQS_H[16],BU20,VDD,AD15,VDDNB,P17,VSS,V33,VSS,BR5
 
L2_CADOUT_H[7],V8,MA_DQS_H[5],BM30,MC_CLK_L[1],AN34,MD_DQS_H[17],R37,VDD,AE2,VDDNB,P19,VSS,V36,VSS,BR8
 
L2_CADOUT_H[8],AH13,MA_DQS_H[6],BM24,MC_CLK_L[2],AL36,MD_DQS_L[0],A18,VDD,AE8,VDDNB,P21,VSS,V39,VSS,BR11
 
L2_CADOUT_H[9],AG11,MA_DQS_H[7],BM18,MC_CLK_L[3],AK34,MD_DQS_L[1],A24,VDD,AE14,VDDNB,P23,VSS,W5,VSS,BR14
 
L2_CADOUT_H[10],AF12,MA_DQS_H[8],T31,MC_CLK_L[4],AJ35,MD_DQS_L[2],A30,VDD,AF4,VDDNB,P25,VSS,W11,VSS,BR17
 
L2_CADOUT_H[11],AE13,MA_DQS_H[9],E17,MC_DATA[0],M16,MD_DQS_L[3],A36,VDD,AF10,VDDNB,P27,VSS,W15,VSS,BR20
 
L2_CADOUT_H[12],AA11,MA_DQS_H[10],E23,MC_DATA[1],M17,MD_DQS_L[4],BR37,VDD,AF13,VDDNB,R14,VSS,W27,VSS,BR23
 
L2_CADOUT_H[13],Y12,MA_DQS_H[11],E29,MC_DATA[2],L20,MD_DQS_L[5],BR31,VDD,AF15,VDDNB,R16,VSS,W29,VSS,BR26
 
L2_CADOUT_H[14],W13,MA_DQS_H[12],E35,MC_DATA[3],L21,MD_DQS_L[6],BR25,VDD,AG6,VDDNB,R18,VSS,W32,VSS,BR29
 
L2_CADOUT_H[15],V11,MA_DQS_H[13],BP38,MC_DATA[4],K15,MD_DQS_L[7],BR19,VDD,AG12,VDDNB,R20,VSS,W35,VSS,BR32
 
L2_CADOUT_L[0],AH9,MA_DQS_H[14],BP32,MC_DATA[5],K16,MD_DQS_L[8],T39,VDD,AG14,VDDNB,R22,VSS,W38,VSS,BR35
 
L2_CADOUT_L[1],AG7,MA_DQS_H[15],BP26,MC_DATA[6],M19,MD_DQS_L[9],B18,VDD,AH2,VDDNB,R24,VSS,Y7,VSS,BR38
 
L2_CADOUT_L[2],AF8,MA_DQS_H[16],BP20,MC_DATA[7],M20,MD_DQS_L[10],B24,VDD,AH8,VDDNB,R26,VSS,Y14,VSS,BT4
 
L2_CADOUT_L[3],AE9,MA_DQS_H[17],R28,MC_DATA[8],M22,MD_DQS_L[11],B30,VDD,AH15,VDDNB,T27,VSS,Y26,VSS,BT7
 
L2_CADOUT_L[4],AA7,MA_DQS_L[0],D18,MC_DATA[9],M23,MD_DQS_L[12],B36,VDD,AJ4,VDDNB,U26,VSS,Y28,VSS,BT10
 
L2_CADOUT_L[5],Y8,MA_DQS_L[1],D24,MC_DATA[10],L26,MD_DQS_L[13],BU37,VDD,AJ10,VDDNB,U28,VSS,AA3,VSS,BT13
 
L2_CADOUT_L[6],W9,MA_DQS_L[2],D30,MC_DATA[11],L27,MD_DQS_L[14],BU31,VDD,AJ14,VDDNB,V27,VSS,AA9,VSS,BT16
 
L2_CADOUT_L[7],V7,MA_DQS_L[3],D36,MC_DATA[12],K21,MD_DQS_L[15],BU25,VDD,AK6,VDDNB,W26,VSS,AA13,VSS,BT19
 
L2_CADOUT_L[8],AH12,MA_DQS_L[4],BM37,MC_DATA[13],K22,MD_DQS_L[16],BU19,VDD,AK12,VDDNB,W28,VSS,AA15,VSS,BT22
 
L2_CADOUT_L[9],AG10,MA_DQS_L[5],BM31,MC_DATA[14],M25,MD_DQS_L[17],R38,VDD,AK13,VDDNB_SENSE,A3,VSS,AA27,VSS,BT25
 
L2_CADOUT_L[10],AF11,MA_DQS_L[6],BM25,MC_DATA[15],M26,MD_ERR_L,AB39,VDD,AK15,VDDR,B14,VSS,AB5,VSS,BT28
 
L2_CADOUT_L[11],AE12,MA_DQS_L[7],BM19,MC_DATA[16],M28,MD_EVENT_L,AP40,VDD,AL2,VDDR,B15,VSS,AB11,VSS,BT31
 
L2_CADOUT_L[12],AA10,MA_DQS_L[8],T30,MC_DATA[17],M29,MD_PAR,AR39,VDD,AL8,VDDR,C13,VSS,AB14,VSS,BT34
 
L2_CADOUT_L[13],Y11,MA_DQS_L[9],E18,MC_DATA[18],L32,MD_RAS_L,AU40,VDD,AL14,VDDR,C14,VSS,AB26,VSS,BT37
 
L2_CADOUT_L[14],W12,MA_DQS_L[10],E24,MC_DATA[19],L33,MD_RESET_L,W37,VDD,AM4,VDDR,BR15,VSS,AB28,VSS,BU3
 
L2_CADOUT_L[15],V10,MA_DQS_L[11],E30,MC_DATA[20],K27,MD_WE_L,AU39,VDD,AM10,VDDR,BR16,VSS,AC7,VSS,BU6
 
L2_CLKIN_H[0],J7,MA_DQS_L[12],E36,MC_DATA[21],K28,M_TEST,W31,VDD,AM13,VDDR,BT14,VSS,AC13,VSS,BU9
 
L2_CLKIN_H[1],J10,MA_DQS_L[13],BP37,MC_DATA[22],M31,M_VREF[0],W40,VDD,AM15,VDDR,BT15,VSS,AC15,VSS,BU12
 
L2_CLKIN_L[0],J8,MA_DQS_L[14],BP31,MC_DATA[23],M32,M_VREF[1],W39,VDD,AN6,VDDR_SENSE,AH27,VSS,AC27,VSS,BU15
 
L2_CLKIN_L[1],J11,MA_DQS_L[15],BP25,MC_DATA[24],M34,M_ZVDDIO[0],W34,VDD,AN12,VDD_SENSE,B2,VSS,AD3,VSS,BU18
 
L2_CLKOUT_H[0],AC9,MA_DQS_L[16],BP19,MC_DATA[25],M35,M_ZVDDIO[1],BE38,VDD,AN14,VLDT,C1,VSS,AD9,VSS,BU21
 
L2_CLKOUT_H[1],AC12,MA_DQS_L[17],R29,MC_DATA[26],L38,PROCHOT_L,BU7,VDD,AP2,VLDT,C2,VSS,AD14,VSS,BU24
 
L2_CLKOUT_L[0],AC8,MA_ERR_L,AB30,MC_DATA[27],L39,PWROK,B8,VDD,AP8,VLDT,C4,VSS,AD26,VSS,BU27
 
L2_CLKOUT_L[1],AC11,MA_EVENT_L,AP31,MC_DATA[28],K33,RESET_L,B6,VDD,AP15,VLDT,C5,VSS,AE5,VSS,BU30
 
L2_CTLIN_H[0],R7,MA_PAR,AR30,MC_DATA[29],K34,RSVD,B9,VDD,AR4,VLDT,C7,VSS,AE11,VSS,BU33
 
L2_CTLIN_H[1],R10,MA_RAS_L,AU31,MC_DATA[30],M37,RSVD,B11,VDD,AR10,VLDT,C8,VSS,AE15,VSS,BU36
 
L2_CTLIN_L[0],R8,MA_RESET_L,W30,MC_DATA[31],M38,RSVD,B12,VDD,AR14,VLDT,C10,VSS,AE27,VSS_SENSE,B3
 
-->
 
 
 
=== Pin Description ===
 
{| class="wikitable sortable"
 
!Signal!!Description
 
|-
 
|MA/MB/MC/MD_ADD[15:0]||DRAM Channel A-D Column/Row Address
 
|-
 
|MA/MB/MC/MD_BANK[2:0]||DRAM Bank Address
 
|-
 
|MA/MB/MC/MD_CAS_L||DRAM Column Address Strobe
 
|-
 
|MA/MB/MC/MD_CHECK[7:0]||DRAM ECC Bits
 
|-
 
|MA/MB/MC/MD_CKE[1:0]||DRAM Clock Enable
 
|-
 
|MA/MB/MC/MD_CLK_H/L[4:0]||DRAM Differential Clock
 
|-
 
|MA/MB/MC/MD_DATA[63:0]||DRAM Data Bus
 
|-
 
|MA/MB/MC/MD_DQS_H/L[17:0]||DRAM Differential Data Strobe
 
|-
 
|MA/MB/MC/MD_ERR_L||
 
|-
 
|MA/MB/MC/MD_EVENT_L||DRAM Thermal Event Status
 
|-
 
|MA/MB/MC/MD_PAR||
 
|-
 
|MA/MB/MC/MD_RAS_L||DRAM Row Address Strobe
 
|-
 
|MA/MB/MC/MD_RESET_L||DRAM Reset
 
|-
 
|MA/MB/MC/MD_WE_L||DRAM Write Enable
 
|-
 
|MA0/MA1_CS_L[1:0]<br/>MB0/MB1_CS_L[1:0]<br/>MC0/MC1_CS_L[1:0]<br/>MD0/MD1_CS_L[1:0]||DRAM Chip Select
 
|-
 
|MA0/MA1/MA2/MA3_ODT[0]<br/>MB0/MB1/MB2/MB3_ODT[0]<br/>MC0/MC1/MC2/MC3_ODT[0]<br/>MD0/MD1/MD2/MD3_ODT[0]||DRAM Enable Pin for On Die Termination
 
|-
 
|M_TEST||
 
|-
 
|M_VREF[1:0]||DRAM Interface Voltage Reference
 
|-
 
|M_ZVDDIO[1:0]||
 
|-
 
|L0/L1/L2/L3_CADIN_H/L[15:0]||HT Link 0-3 Differential Command/Address/Data Input
 
|-
 
|L0/L1/L2/L3_CADOUT_H/L[15:0]||HT Link 0-3 Differential Command/Address/Data Output
 
|-
 
|L0/L1/L2/L3_CLKIN_H/L[1:0]||HT Link 0-3 Differential Clock Input
 
|-
 
|L0/L1/L2/L3_CLKOUT_H/L[1:0]||HT Link 0-3 Differential Clock Output
 
|-
 
|L0/L1/L2/L3_CTLIN_H/L[1:0]||HT Link 0-3 Differential Control Input
 
|-
 
|L0/L1/L2/L3_CTLOUT_H/L[1:0]||HT Link 0-3 Differential Control Output
 
|-
 
|LDTSTOP_L||HT Stop Control Input for power management and link width and frequency change
 
|-
 
|HTREF0,||? HT Compensation Resistor to VSS, VLDT
 
|-
 
|CLKIN_H/L||Differential PLL Reference Clock
 
|-
 
|PWROK||Voltages and CLKIN have reached specified operation
 
|-
 
|RESET_L||Processor Reset
 
|-
 
|ALERT_L||
 
|-
 
|PROCHOT_L||Processor in {{abbr|HTC}}-active state
 
|-
 
|SIC||Sideband Interface Clock<ref>The Sideband Interface (SBI) a.k.a. {{abbr|APML}} is a {{abbr|SMBus}} interconnect to the processor's {{abbr|SB-RMI}} and {{abbr|SB-TSI}} interfaces.</ref>
 
|-
 
|SID||Sideband Interface Data
 
|-
 
|THERMTRIP_L||{{x86|Thermal protection|Temperature Trip}}
 
|-
 
|DBRDY||
 
|-
 
|DBREQ_L||Debug Request input to JTAG controller
 
|-
 
|TCK||{{abbr|JTAG}} Clock
 
|-
 
|TDI||JTAG Data Input
 
|-
 
|TDO||JTAG Data Output
 
|-
 
|TMS||JTAG Mode Select
 
|-
 
|TRST_L||JTAG Reset
 
|-
 
|TEST*||Test Pins
 
|-
 
|SVC||Serial VID Interface Clock
 
|-
 
|SVD||Serial VID Interface Data
 
|-
 
|VDD||Core power supply
 
|-
 
|VDD_SENSE||VDD voltage monitor pin
 
|-
 
|VDDA||
 
|-
 
|VDDIO||DRAM I/O ring power supply
 
|-
 
|VDDIO_FB_H/L||Differential feedback to VDDIO regulator
 
|-
 
|VDDNB||Northbridge power supply
 
|-
 
|VDDNB_SENSE||VDDNB voltage monitor pin
 
|-
 
|VDDR||VDDR power supply
 
|-
 
|VDDR_SENSE||VDDR voltage monitor pin
 
|-
 
|VLDT||HyperTransport I/O ring power supply
 
|-
 
|VLDT_SENSE||VLDT voltage monitor pin
 
|-
 
|VSS||Ground
 
|-
 
|VSS_SENSE||VSS sense output for voltage regulators
 
|-
 
|SA[2:0]||Socket Identifier
 
|-
 
|CPU_PRESENT_L||CPU Presence Indicator
 
|-
 
|RSVD||Reserved
 
|}
 
<references/>
 
  
== Bibliography ==
+
== References ==
* {{cite techdoc|title=Family 10h AMD Opteron Processor Product Data Sheet|url=https://www.amd.com/system/files/TechDocs/40036.pdf|publ=AMD|pid=40036|rev=3.04|date=2010-06-22}}
+
* [https://www.amd.com/system/files/TechDocs/40036.pdf "Family 10h AMD Opteron Processor Product Data Sheet"], AMD Publ. #40036, Rev. 3.04, June 22, 2010
* {{cite techdoc|title=Family 15h Models 00h-0Fh AMD Opteron Processor Product Data Sheet|url=https://www.amd.com/system/files/TechDocs/49687_15h_Mod_00h-0Fh_Opteron_PDS.pdf|publ=AMD|pid=49687|rev=3.01|date=2012-10-10}}
+
* [https://www.amd.com/system/files/TechDocs/49687_15h_Mod_00h-0Fh_Opteron_PDS.pdf "Family 15h Models 00h-0Fh AMD Opteron Processor Product Data Sheet"], AMD Publ. #49687, Rev. 3.01, October 10, 2012
* {{cite techdoc|title=BIOS and Kernel Developer’s Guide (BKDG) For AMD Family 10h Processors|url=https://www.amd.com/system/files/TechDocs/31116.pdf|publ=AMD|pid=31116|rev=3.62|date=2013-01-14}}
+
* [https://www.amd.com/system/files/TechDocs/31116.pdf "BIOS and Kernel Developer’s Guide (BKDG) For AMD Family 10h Processors"], AMD Publ. #31116, Rev. 3.62, January 14, 2013
* {{cite techdoc|title=BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors|url=https://www.amd.com/system/files/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf|publ=AMD|pid=42301|rev=3.14|date=2013-01-28}}
+
* [https://www.amd.com/system/files/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf "BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors"], AMD Publ. #42301, Rev. 3.14, January 28, 2013
* {{cite techdoc|title=Revision Guide for AMD Family 10h Processors|url=https://www.amd.com/system/files/TechDocs/41322_10h_Rev_Gd.pdf|publ=AMD|pid=41322|rev=3.92|date=2012-03}}
+
* [https://www.amd.com/system/files/TechDocs/41322_10h_Rev_Gd.pdf "Revision Guide for AMD Family 10h Processors"], AMD Publ. #41322, Rev. 3.92, March 2012
* {{cite techdoc|title=Revision Guide for AMD Family 15h Models 00h-0Fh Processors|url=https://www.amd.com/system/files/TechDocs/48063_15h_Mod_00h-0Fh_Rev_Guide.pdf|publ=AMD|pid=48063|rev=3.24|date=2014-09-30}}
+
* [https://www.amd.com/system/files/TechDocs/48063_15h_Mod_00h-0Fh_Rev_Guide.pdf "Revision Guide for AMD Family 15h Models 00h-0Fh Processors"], AMD Publ. #48063, Rev. 3.24, September 30, 2014
* {{cite article|authors=Conway, Pat;Kalyanasundharam, Nathan;Donley, Gregg;Lepak, Kevin;Hughes, Bill|title=Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor|date=2010-04-12|journal=IEEE Micro|volume=30|issue=2|pages=16-29|doi=10.1109/MM.2010.31}}
+
* Conway, Pat; Kalyanasundharam, Nathan; Donley, Gregg; Lepak, Kevin; Hughes, Bill (2010). <i>Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor</i>. IEEE Micro. 30 (2): 16-29. doi:[https://doi.org/10.1109/MM.2010.31 10.1109/MM.2010.31]
 
* Financial Analyst Day Presentation, November 11, 2009
 
* Financial Analyst Day Presentation, November 11, 2009
  

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Facts about "Socket G34 - AMD"
designerAMD +
first launchedMarch 29, 2010 +
instance ofpackage +
market segmentServer +
microarchitectureK10 +, Bulldozer + and Piledriver +
nameSocket G34 +
packageLGA-1944 +
package contacts1,944 +
package length60 mm (6 cm, 2.362 in) +
package pitch1 mm (0.0394 in) +
package typeFC-OLGA +
package width42.5 mm (4.25 cm, 1.673 in) +
socketSocket G34 +
tdp140 W (140,000 mW, 0.188 hp, 0.14 kW) +